AD5328ARUZ Analog Devices Inc, AD5328ARUZ Datasheet - Page 15

• Manufacturer Part Number: AD5328ARUZ
• Description: IC DAC 12BIT OCTAL W/BUF 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5328ARUZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 167kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 1mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD5308/AD5318/AD5328 are octal resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains eight output buffer ampli-
fiers and is written to via a 3-wire serial interface. They operate
from single supplies of 2.5 V to 5.5 V and the output buffer
amplifiers provide rail-to-rail output swing with a slew rate of
0.7 V/μs. DAC A, DAC B, DAC C, and DAC D share a common
reference input, V
share a common reference input, V
input can be buffered to draw virtually no current from the
reference source, can be unbuffered to give a reference input
range from 0.25 V to V
have a power-down mode in which all DACs can be turned off
individually with a high impedance output.
DIGITAL-TO-ANALOG CONVERTER
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the V
sponding DAC. Figure 29 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for AD5308 (8 bits)
0 to 1023 for AD5318 (10 bits)
0 to 4095 for AD5328 (12 bits)
N is the DAC resolution.
DAC Reference Inputs
There is a reference pin for each quad of DACs. The reference
inputs can be buffered from V
with the buffered input is the high impedance it presents to the
voltage source driving it. However, if the unbuffered mode is
used, the user can have a reference voltage as low as 0.25 V and
as high as V
and footroom of the reference amplifier.
REGISTER
V
INPUT
DD
V
OUT
REF
=
pin provides the reference voltage for the corre-
V
DD
DD
V
Figure 29. Single DAC Channel Architecture
REF
BUF
since there is no restriction due to the headroom
REGISTER
2
REF
DAC
N
×
ABCD. DAC E, DAC F, DAC G, and DAC H
D
DD
, or can come from V
V
RESISTOR
REF
STRING
DD
ABCD
, or unbuffered. The advantage
REF
REFERENCE
BUFFER
EFGH. Each reference
BUFFER AMPLIFIER
(GAIN = +1 OR +2)
GAIN MODE
DD
OUTPUT
. The devices
V
Rev. F | Page 15 of 28
OUT
A
If there is a buffered reference in the circuit (for example, the
REF192), there is no need to use the on-chip buffers of the
AD5308/AD5318/AD5328. In unbuffered mode, the input
impedance is still large at typically 45 kΩ per reference input
for 0 V to V
RESISTOR STRING
The resistor-string section is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of V
error, and the gain error.
If a gain of 1 is selected (gain bit = 0), the output range is
0.001 V to V
If a gain of 2 is selected (gain bit = 1), the output range is
0.001 V to 2 V
output is limited to V
The output amplifier is capable of driving a load of 2 kΩ to
GND or V
source and sink capabilities of the output amplifier can be seen
in the plot in Figure 14.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 μs.
DD
REF
REF
, in parallel with 500 pF to GND or V
REF
mode and 22 kΩ for 0 V to 2 V
.
. Because of clamping, however, the maximum
REF
R
R
R
R
R
, the gain of the output amplifier, the offset
DD
Figure 30. Resistor String
− 0.001 V.
AD5308/AD5318/AD5328
TO OUTPUT
AMPLIFIER
REF
mode.
DD
. The