AD5327BRUZ Analog Devices Inc, AD5327BRUZ Datasheet - Page 18

• Manufacturer Part Number: AD5327BRUZ
• Description: IC DAC 12BIT QUAD 2.5V 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5327BRUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 500µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5307/AD5317/AD5327
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC . The SCLK and DIN input buffers
are powered down on the rising edge of SYNC .
DAISY CHAINING
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial readback.
By connecting the DCEN (daisy-chain enable) pin high, the
daisy-chain mode is enabled. It is tied low in the case of
standalone mode. In daisy-chain mode, the internal gating on
SCLK is disabled. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 16 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting
this line to the DIN input on the next DAC in the chain, a
multi-DAC interface is constructed. Each DAC in the system
requires 16 clock pulses; therefore, the total number of clock
cycles must equal 16N, where N is the total number of devices
in the chain. When the serial transfer to all devices is complete,
SYNC should be taken high. This prevents any further data
from being clocked into the input shift register.
A continuous SCLK source can be used if SYNC is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC can be taken high some time later.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.
DOUBLE-BUFFERED INTERFACE
The AD5307/AD5317/AD5327 DACs have double-buffered
interfaces consisting of two banks of registers: input registers
and DAC registers. The input registers are connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC registers contain the digital code used by the resistor
strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them.
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The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then, by bringing
LDAC low when writing to the remaining DAC input register,
all outputs update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5307/AD5317/AD5327,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
LOAD DAC INPUT (LDAC)
LDAC transfers data from the input registers to the DAC
registers and therefore updates the outputs. Use of the LDAC
function enables double buffering of the DAC data, GAIN, and
BUF. There are two LDAC modes: synchronous and asynchronous.
Synchronous Mode
In this mode, the DAC registers are updated after new data is
read from on the falling edge of the 16th SCLK pulse. LDAC
can be tied permanently low or pulsed as in Figure 3.
Asynchronous Mode
In this mode, the outputs are not updated at the same time that
the input registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
POWER-DOWN MODE
The AD5307/AD5317/AD5327 have low power consumption,
typically dissipating 1.2 mW with a 3 V supply and 2.5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down mode,
which is selected by taking the PD pin low.
When the PD pin is high, all DACs work normally with a typical
power consumption of 500 μA at 5 V (400 μA at 3 V). However,
in power-down mode, the supply current falls to 300 nA at 5 V
(90 nA at 3 V) when all DACs are powered down. Not only does
the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it an open
circuit. This has the advantage that the output is three-state
while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. The output stage is illustrated in Figure 36.
The bias generator, output amplifiers, resistor string, and all
other associated linear circuitry are shut down when the power-
down mode is activated. However, the contents of the registers
are unaffected when in power-down. In fact, it is possible to
load new data to the input registers and DAC registers during
power-down. The DAC outputs update as soon as PD goes high.