AD5541ARZ Analog Devices Inc, AD5541ARZ Datasheet - Page 15

IC DAC 16BIT SERIAL IN 8-SOIC

AD5541ARZ

Manufacturer Part Number
AD5541ARZ
Description
IC DAC 16BIT SERIAL IN 8-SOIC
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD5541ARZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Design Resources
How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
Settling Time
1µs
Number Of Bits
16
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
6.05mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resolution (bits)
16bit
Sampling Rate
1.5MSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
2.7V To 5.5V
Supply Current
300µA
Digital Ic Case Style
SOIC
Number Of Channels
1
Resolution
16b
Interface Type
SER 3W SPI QSPI UW
Single Supply Voltage (typ)
5V
Dual Supply Voltage (typ)
Not RequiredV
Architecture
R-2R
Power Supply Requirement
Single
Output Type
Voltage
Single Supply Voltage (min)
4.5V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5541/AD5542 are Schmitt-triggered so
that they can accept slow transitions on the digital input lines.
This makes these parts ideal for industrial applications where it
may be necessary to isolate the DAC from the controller via
optocouplers. Figure 29 illustrates such an interface.
POWER
SCLK
DIN
CS
Figure 29. AD5541/AD5542 in an Optocoupler Interface
10kΩ
10kΩ
10kΩ
V
V
V
DD
DD
DD
REGULATOR
SCLK
CS
DIN
5V
AD5541/AD5542
GND
V
DD
V
OUT
10µF
0.1µF
Rev. E | Page 15 of 20
DECODING MULTIPLE AD5541/AD5542s
The CS pin of the AD5541/AD5542 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There is
some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels.
ADDRESS
ENABLE
CODED
SCLK
DIN
Figure 30. Addressing Multiple AD5541/AD5542s
EN
DECODER
DGND
V
DD
Figure 30
shows a typical circuit.
AD5541/AD5542
AD5541/AD5542
AD5541/AD5542
AD5541/AD5542
AD5541/AD5542
CS
DIN
SCLK
CS
DIN
SCLK
CS
DIN
SCLK
CS
DIN
SCLK
V
V
V
V
OUT
OUT
OUT
OUT

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