MAX542AESD+ Maxim Integrated Products, MAX542AESD+ Datasheet - Page 8
![IC DAC 16BIT SER VOUT 5V 14-SOIC](/photos/6/57/65727/175-14-soic_sml.jpg)
MAX542AESD+
Manufacturer Part Number
MAX542AESD+
Description
IC DAC 16BIT SER VOUT 5V 14-SOIC
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX541CCSA.pdf
(12 pages)
Specifications of MAX542AESD+
Settling Time
1µs
Number Of Bits
16
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
The MAX541/MAX542’s digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on CS’s low-to-high transition (Figure 3a). Note
that if CS is not kept low during the entire 16 SCLK
cycles, data will be corrupted. In this case, reload the
DAC latch with a new 16-bit word.
Alternatively, for the MAX542, LDAC allows the DAC
latch to update asynchronously by pulling LDAC low
after CS goes high (Figure 3b). Hold LDAC high during
the data-loading sequence.
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Figure 3a. MAX541/MAX542 3-Wire Interface Timing Diagram ( LDAC = DGND for MAX542)
Figure 3b. MAX542 4-Wire Interface Timing Diagram
8
_______________________________________________________________________________________
LDAC
SCLK
SCLK
DIN
CS
DIN
CS
D15 D14 D13 D12 D11 D10 D9 D8
D15
MSB
D14 D13 D12 D11 D10 D9
MSB
Digital Interface
D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
The MAX541/MAX542 operate with external voltage ref-
erences from 2V to 3V. The reference voltage deter-
mines the DAC’s full-scale output voltage. Kelvin
connections are provided with the MAX542 for optimum
performance.
The MAX541/MAX542 have a power-on reset circuit to
set the DAC’s output to 0V in unipolar mode when V
is first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after a loss of power. In bipolar
mode, the DAC output is set to -V
LSB
LSB
UPDATED
DAC
UPDATED
DAC
External Reference
REF
Power-On Reset
.
DD