AD5623RBRMZ-3 Analog Devices Inc, AD5623RBRMZ-3 Datasheet - Page 7
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AD5623RBRMZ-3
Manufacturer Part Number
AD5623RBRMZ-3
Description
IC DAC NANO 12BIT DUAL 10-MSOP
Manufacturer
Analog Devices Inc
Series
nanoDAC™r
Specifications of AD5623RBRMZ-3
Data Interface
Serial
Settling Time
3µs
Number Of Bits
12
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
5mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Resolution (bits)
12bit
Sampling Rate
287kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
2.7V To 3.6V, 4.5V To 5.5V
Supply Current
800µA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD5623RBRMZ-3
Manufacturer:
ADI
Quantity:
1 500
Part Number:
AD5623RBRMZ-3
Manufacturer:
ADI/亚德诺
Quantity:
20 000
TIMING CHARACTERISTICS
All input signals are specified with t
V
Table 5.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
TIMING DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Guaranteed by design and characterization, not production tested.
Maximum SCLK frequency is 50 MHz at V
2
DD
= 2.7 V to 5.5 V; all specifications T
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
LDAC
LDAC
SYNC
SCLK
V
CLR
OUT
DIN
1
2
Limit at T
V
20
9
9
13
5
5
0
15
13
0
10
15
5
0
300
DD
= 2.7 V to 5.5 V
MIN
t
DD
8
t
, T
10
R
= 2.7 V to 5.5 V.
= t
MAX
DB23
MIN
F
= 1 ns/V (10% to 90% of V
t
13
t
to T
4
t
5
t
15
MAX
t
6
, unless otherwise noted.
t
3
Figure 2. Serial Write Operation
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Rev. D | Page 7 of 32
t
1
t
2
DD
DB0
) and timed from a voltage level of (V
t
t
14
7
t
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
9
1
t
11
t
12
AD5623R/AD5643R/AD5663R
IL
+ V
IH
)/2.