AD9788BSVZ Analog Devices Inc, AD9788BSVZ Datasheet - Page 4

• Manufacturer Part Number: AD9788BSVZ
• Description: IC DAC 16BIT 800MSPS 100TQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9788BSVZ

• Data Interface: Serial
• Design Resources: Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 450mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 800MSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Settling Time: 0.02us
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Integral Nonlinearity Error: ±3.7LSB
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9788-EBZ - BOARD EVAL FOR AD9788
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

AD9785/AD9787/AD9788
DIGITAL SPECIFICATIONS
T
otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
LVDS INPUT (SYNC_I+, SYNC_I−)
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
DAC CLOCK INPUT (REFCLK+, REFCLK–)
MAXIMUM INPUT DATA RATE
SERIAL PERIPHERAL INTERFACE
INPUT DATA
MIN
REFCLK Frequency Range, PLL Enabled
Input V
Input V
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate (f
Setup Time, SYNC_I to DAC Clock
Hold Time, SYNC _I to DAC Clock
Output Voltage High, V
Output Voltage Low, V
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, Single-Ended, R
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time, SPI_SDIO to SCLK
Hold Time, SPI_SDIO to SCLK
Setup Time, SPI_CSB to SCLK
Data Valid, SPI_SDO to SCLK
Setup Time, Input Data to DATACLK
Hold Time, Input Data to DATACLK
Setup Time, Input Data to REFCLK
Hold Time, Input Data to REFCLK
to T
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
DVDD18 = 1.8 V ± 5%
DVDD18 = 1.9 V ± 5%
DVDD18 = 1.8 V ±5%
DVDD18 = 1.9 V ± 5%
MAX
IN
IN
Logic High
Logic Low
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
SYNC_I
OA
IA
= f
OA
OS
or V
or V
or V
DATA
IB
OB
)
OB
IDTH
IDTHH
OD
|
− V
O
IDTHL
IN
Test Conditions/Comments
SYNC_I+ = V
SYNC_O+ = V
All modes, −40°C to +85°C
Rev. A | Page 4 of 64
1A
OA
, SYNC_I− = V
, SYNC_O− = V
1
1B
OB
, 100 Ω termination
OUTFS
= 20 mA, maximum sample rate, unless
Min
825
–100
80
825
1025
150
1150
80
112.5
−0.25
2.0
30
0.45
0.25
400
300
800
900
30
200
225
100
40
12.5
12.5
2.8
0.0
3.0
10.0
460
−1.5
2.4
Typ
20
200
100
800
400
250
250
Max
0.8
1575
+100
120
1575
250
1250
120
1600
500
250
Unit
V
V
mV
mV
mV
Ω
MHz
ns
ns
mV
mV
mV
mV
Ω
mV
mV
MHz
MHz
MHz
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns