MAX510BCPE+ Maxim Integrated Products, MAX510BCPE+ Datasheet - Page 10

• Manufacturer Part Number: MAX510BCPE+
• Description: IC DAC QUAD SRL 8BIT R-R 16-DIP
• Manufacturer: Maxim Integrated Products

Specifications of MAX510BCPE+

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 842mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Number Of Dac Outputs: 4
• Resolution: 8 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): - 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 5 mA
• Voltage Reference: 4 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
10
A1
0
0
1
1
0
0
1
1
X
X
0
1
1
______________________________________________________________________________________
NOTE: TIMING SPECIFICATION t
SCLK
CS
DIN
DOUT
LDAC
A0
0
1
0
1
0
1
0
1
0
1
X
1
0
12-Bit Serial Word
C1
t
0
0
0
0
1
1
1
1
0
0
1
1
1
CSH0
CLL
IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
t
CSS
C0
1
1
1
1
1
1
1
1
0
0
0
0
0
t
DS
t
DH
D7 . . . . . . . . D0
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
t
CH
t
DO
t
CL
LDAC
1
1
1
1
1
1
1
1
X
X
X
X
X
• • •
• • •
• • •
• • •
• • •
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
Update all DACs from shift register.
No Operation (NOP), shifts data in shift register.
“LDAC” Command, all DACs updated from respective
input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
t
CSH1
t
CSH2
Function
t
CLL
t
LDW