TC1321EOA Microchip Technology, TC1321EOA Datasheet - Page 9

• Manufacturer Part Number: TC1321EOA
• Description: IC DAC 10BIT 2WIRE I2C 8SOIC
• Manufacturer: Microchip Technology

Specifications of TC1321EOA

• Number Of Converters: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Settling Time: 10µs
• Number Of Bits: 10
• Data Interface: I²C
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Resolution: 10 bit
• Interface Type: Serial (2-Wire, I2C)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
The Serial Clock input (SCL) and bi-directional data
port (SDA) form a 2-wire bi-directional serial port for
programming and interrogating the TC1321. The
following conventions are used in this bus architecture.
TABLE 4-1:
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the master, which
provides the clock signal for all transfers. The TC1321
always operates as a slave. The serial protocol is
illustrated in
phases; all bytes are transferred MSB first. Accesses
are initiated by a START condition (START), followed
by a device-address byte and one or more data bytes.
The device-address byte includes a Read/Write
selection bit. Each access must be terminated by a
STOP
Acknowledge (ACK) confirms receipt of each byte.
Note that SDA can change only during periods when
SCL is LOW (SDA changes while SCL is HIGH are
reserved for START and STOP conditions).
 2010 Microchip Technology Inc.
Transmitter The device sending data to the bus.
Receiver
Master
Slave
START
STOP
ACK
Busy
Not Busy
Data Valid
Term
Condition
SERIAL PORT OPERATION
The device receiving data from the bus.
The device that controls the bus: initiating
transfers (START), generating the clock, and
terminating transfers (STOP)
The device addressed by the master.
A unique condition signaling the beginning of
a transfer, indicated by SDA falling (High -
Low) while SCL is high.
A unique condition signaling the end of a
transfer, indicated by SDA rising (Low - High)
while SCL is high.
A receiver acknowledges the receipt of each
byte with this unique condition. The receiver
drives SDA low during SCL, high of the ACK
clock pulse.The master provides the clock
pulse for the ACK cycle.
Communication is not possible because the
bus is in use.
When the bus is IDLE, both SDA and SCL will
remain high.
The state of SDA must remain stable during
the High period of SCL in order for a data bit
to be considered valid. SDA only changes
state while SCL is low during normal data
transfers. See START and STOP conditions.
Figure
TC1321 SERIAL BUS
CONVENTIONS
(STOP).
4-1. All data transfers have two
Explanation
A
convention
called
4.1
The TC1321 continuously monitors the SDA and SCL
lines for a START condition (a HIGH to LOW transition
of SDA while SCL is HIGH), and will not respond until
this condition is met.
4.2
Immediately following the START condition, the host
must transmit the address byte to the TC1321. The
7-bit SMBus address for the TC1321 is 1001000. The
7-bit address transmitted in the serial bit stream must
match for the TC1321 to respond with an Acknowledge
(indicating the TC1321 is on the bus and ready to
accept data). The eighth bit in the Address Byte is a
Read-Write bit. This bit is a 1 for a read operation or 0
for a write operation. During the first phase of any
transfer, this bit will be set = 0 to indicate that the
command byte is being written.
4.3
Acknowledge (ACK) provides a positive handshake
between the host and the TC1321. The host releases
SDA after transmitting eight bits, then generates a ninth
clock cycle to allow the TC1321 to pull the SDA line
LOW to Acknowledge that it successfully received the
previous eight bits of data or address.
4.4
After a successful ACK of the address byte, the host
must transmit the data byte to be written or clock out
the data to be read. (See the appropriate timing
diagrams.) ACK will be generated after a successful
write of a data byte into the TC1321.
4.5
Communications must be terminated by a STOP
condition (a LOW to HIGH transition of SDA while SCL
is HIGH). The STOP condition must be communicated
by the transmitter to the TC1321. Refer to
for serial bus timing.
START Condition (START)
Address Byte
Acknowledge (ACK)
Data Byte
Stop Condition (STOP)
TC1321
DS21387C-page 9
Figure
4-1,