LTC1665IGN#PBF Linear Technology, LTC1665IGN#PBF Datasheet - Page 9

• Manufacturer Part Number: LTC1665IGN#PBF
• Description: IC D/A CONV 8BIT OCTAL 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC1665IGN#PBF

• Settling Time: 30µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Number Of Channels: 8
• Resolution: 8b
• Interface Type: Serial
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SSOP N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATIO
Table 1a. LTC1665 Input Word
Table 1b. LTC1660 Input Word
A3 A2 A1
Address/Control
CS/LD
CS/LD
A3 A2 A1
Address/Control
D
D
SCK
SCK
OUT
OUT
D
D
IN
IN
(ENABLE CLK)
(ENABLE CLK)
A0 D7 D6 D5 D4 D3 D2 D1 D0 X3
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1
U
A3
A3
Input Code
A3
A3
ADDRESS/CONTROL
ADDRESS/CONTROL
1
1
Input Code
A2
A2
A2
A2
2
2
A1
A1
A1
A1
3
3
A0
A0
Figure 2a. LTC1665 Register Loading Sequence
Figure 2b. LTC1660 Register Loading Sequence
A0
A0
4
4
D7
D9
D7
D9
5
5
Don’t Care
X2
D0
D6
D8
D6
D8
INPUT WORD W
INPUT WORD W
6
6
X1 X0
X1 X0
Don’t
Care
D5
D7
D5
D7
7
7
INPUT WORD W
INPUT WORD W
D4
D6
INPUT CODE
D4
D6
–1
–1
8
8
chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to D
then pulled high, updating all of them simultaneously.
Sleep Mode
DAC address 1110
instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
D3
D5
INPUT CODE
D3
D5
9
9
0
D2
0
D4
D2
D4
10
10
D1
D3
D1
D3
11
11
D0
D2
D0
D2
12
12
X3
D1
b
D1
X3
is reserved for the special Sleep
13
13
LTC1665/LTC1660
D0
X2
DON’T CARE
X2
D0
14
14
X1
X1
IN
DON’T CARE
X1
X1
15
15
of the first chip; CS/LD is
X0
X0
X0
X0
16
16
A3
A3
INPUT WORD W
INPUT WORD W
(UPDATE OUTPUT)
(UPDATE OUTPUT)
1665/60 F02a
1665/60 F02b
0
0
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