LTC1329ACS8-50#TRPBF Linear Technology, LTC1329ACS8-50#TRPBF Datasheet - Page 4

• Manufacturer Part Number: LTC1329ACS8-50#TRPBF
• Description: IC D/A CONV 8BIT MICROPWR 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1329ACS8-50#TRPBF

• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 840µW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

LTC1329-10/
LTC1329-50/LTC1329A-50
TYPICAL PERFORMANCE CHARACTERISTICS
I
the DAC current output can be biased from – 15V to 2V or
– 15V to 2.5V respectively.
V
supply must be kept free from noise and ripple by bypass-
ing directly to the ground plane.
SHDN (Pin 3): Shutdown. A logic low puts the chip
into Shutdown mode. The digital setting for the DAC is
retained.
CLK (Pin 4): Shift Clock. This clock synchronizes the serial
data in 3-wire mode. This pin has a Schmitt trigger input.
4
PIN
OUT
–0.1
–0.2
–0.3
–0.4
–0.5
CC
–0.2
–0.4
–0.6
–0.8
–1.0
0.5
0.4
0.3
0.2
0.1
1.0
0.8
0.6
0.4
0.2
0
0
U
–15
(Pin 2): Voltage Supply (2.7V
LTC1329-10/LTC1329-50
Bias Voltage Rejection
(Full-Scale Current)
(Pin 1): DAC Current Output. In 3.3V or 5V systems,
0
LTC1329-50 INL vs Code
T
V
V(I
T
V
FUNCTIONS
A
A
CC
CC
–12
32
= 25 C
OUT
= 25 C
= 3.3V
= 3.3V
) = 0.45V
U
64
I
–9
OUT
96
BIAS VOLTAGE (V)
–6
CODE
LTC1329-10
128 160
LTC1329-50
–3
U
0
192 224 256
W
1329 • TPC04
3
1329 G07
U
6
V
CC
–10
–20
–30
–40
–50
–1
–2
–3
50
40
30
20
10
3
2
1
0
0
–15
6.5V). This
LTC1329-10/LTC1329-50 Full-
Scale Current vs Temperature
0
LTC1329-10/LTC1329-50
Bias Voltage Rejection
(Zero-Scale Current)
V
V(I
CC
–12
10
OUT
= 3.3V
) = 0.45V
LTC1329-10
LTC1329-50
I
–9
20
OUT
TEMPERATURE ( C)
LTC1329-10
BIAS VOLTAGE (V)
–6
30
CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low
on this CS pin enables the LTC1329. Upon power-up, a
logic high at CS puts the chip into pulse mode. If CS ever
goes low, the chip is configured in 3-wire mode until the
next power is cycled.
GND (Pin 6): Ground. Ground should be tied directly to a
ground plane.
D
data is shifted into D
mode, upon power-up a logic high at D
into increment-only mode. If D
40
–3
IN
LTC1329-50
(UP/DN)(Pin 7): Data Input. In 3-wire mode, the DAC
50
0
60
3
1329 G05
1329 G08
70
6
IN
on the rising edge of CLK. In pulse
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
–1
–2
2
1
0
2.7
0
LTC1329-10/LTC1329-50
Supply Voltage Rejection
Maximum I
vs Supply Voltage
T
V(I
T
I
A
OUT
A
3.2
OUT
= 25 C
1
= 25 C
= FULL-SCALE CURRENT
) = 0.45V
3.7
IN
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
2
OUT
4.2
ever goes low, the
3
IN
Bias Voltage
LTC1329-50
4.7
puts the counter
4
5.2
LTC1329-10
5
5.7
1329 • TPC09
6
6.2
1329 G06
6.7
7