LTC2624CGN Linear Technology, LTC2624CGN Datasheet - Page 9

• Manufacturer Part Number: LTC2624CGN
• Description: IC DAC 12BIT QUAD R-R OUT 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2624CGN

• Settling Time: 7µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 10mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(LTC2624/LTC2624-1)
TYPICAL PERFORMANCE CHARATERISTICS
PIN FUNCTIONS
GND (Pin 1): Analog Ground.
REF LO (Pin 2): Reference Low. The voltage at this pin
sets the zero scale (ZS) voltage of all DACs. This pin can
be raised up to 1V above ground at V
above ground at V
REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Refer-
ence Voltage Inputs for each DAC. REF x sets the full scale
voltage of the DACs. 0V ≤ REF x ≤ V
V
Outputs. The output range is from REF LO to REF x.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When
CS/LD is low, SCK is enabled for shifting data on SDI into
the register. When CS/LD is taken high, SCK is disabled
and the specifi ed command (see Table 1) is executed.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK.
OUT A
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
0
Integral Nonlinearity (INL)
V
V
to V
CC
REF
= 5V
= 4.096V
OUT D
1024
(Pins 4, 5, 13, 14): DAC Analog Voltage
CC
CODE
2048
= 3V.
3072
2604 G31
4095
CC
CC
.
= 5V or 100mV
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
0
Differential Nonlinearity (DNL)
0
V
V
CC
REF
= 5V
= 4.096V
1024
CODE
2048
The LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/
LTC2624-1 accept input word lengths of either 24 or
32 bits.
SDO (Pin 10): Serial Interface Data Output. This pin is
used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising
edges before being output at the next falling edge. SDO
is an active output and does not go high impedance, even
when CS/LD is taken to a logic high level.
CLR (Pin 11): Asynchronous Clear Input. A logic low at
this level-triggered input clears all registers and causes
the DAC voltage outputs to drop to 0V for the LTC2604/
LTC2614/LTC2624. A logic low at this input sets all registers
to midscale code and causes the DAC voltage outputs to
go to midscale for the LTC2604-1/LTC2614-1/LTC2624-1.
CMOS and TTL compatible.
V
CC
LTC2604/LTC2614/LTC2624
(Pin 16): Supply Voltage Input. 2.5V ≤ V
3072
2604 G32
4095
1mV/DIV
2V/DIV
CS/LD
V
OUT
Settling to ±1LSB
V
1/4-SCALE TO 3/4-SCALE STEP
R
AVERAGE OF 2048 EVENTS
CC
L
= 2k, C
= 5V, V
L
REF
= 200pF
= 4.096V
2μs/DIV
6.8μs
CC
≤ 5.5V.
2604fd
9
2604 G33