LTC1660CGN Linear Technology, LTC1660CGN Datasheet - Page 8

• Manufacturer Part Number: LTC1660CGN
• Description: IC D/A CONV 10BIT OCTAL 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC1660CGN

• Settling Time: 30µs
• Number Of Bits: 10
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
LTC1665/LTC1660
TI I G DIAGRA
Transfer Function
The transfer function is
where k is the decimal equivalent of the binary DAC input
code and V
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.2V
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
8
W
V
V
OUT IDEAL
OUT IDEAL
CS/LD
D
SCK
OUT
D
U
IN
(
(
V
REF
REF
)
)
is the voltage at REF (Pin 6).
U
V
256
1024
CC
t
k
5
k
CC
+ 0.2V (see Absolute Maximum
t
V
(Pin 16) is in transition.
9
REF
V
REF
W
for the LTC
for the LTC
A3
t
7
t
1
A3
t
1665
2
1660
A2
A2
t
8
Figure 1
t
3
Serial Interface
Referring to Figure 2a (2b): With CS/LD held low, data on
the D
positive edge of SCK. The 4-bit DAC address, A3-A0, is
loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word and
causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note: SCK
must be low before CS/LD is pulled low.
The buffered serial output of the shift register is available
on the D
appears on D
to D
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, D
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each D
last) to D
register. The SCK and CS/LD signals are common to all
A1
t
4
A1
IN
IN
.
input is shifted into the 16-bit shift register on the
OUT
IN
of the next chip, forming a single 16 m -bit shift
OUT
pin, which swings from GND to V
X1
16 positive SCK edges after being applied
X1
X0
X0
t
6
IN
t
11
and CS/LD) by
OUT
A3
(except the
1665/60 F01
CC
. Data