LTC1454CS Linear Technology, LTC1454CS Datasheet - Page 7

• Manufacturer Part Number: LTC1454CS
• Description: IC D/A CONV 12BIT R-R DUAL16SOIC
• Manufacturer: Linear Technology

Specifications of LTC1454CS

• Settling Time: 14µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 3.5mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DEFI ITIO S
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
does not imply linearity.
Full-Scale Voltage (V
when all bits are set to 1.
Voltage Offset Error (V
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
V
OS
U
NEGATIVE
= V
n
OFFSET
) that divide the full-scale range. The resolution
VOLTAGE
OUT
OUTPUT
Figure 1. Effect of Negative Offset
0V
– (Code)(V
U
FS
OS
): This is the output of the DAC
DAC CODE
): The theoretical voltage at the
FS
)/(2
n
– 1)
LTC1454/5 • F01
Nominal LSBs:
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset speci-
fication. The INL error at a given input code is calculated
as follows:
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
LSB = (V
LTC1454
LTC1454L
INL
V
DNL
OUT
V
OUT
= [V
= The output voltage of the DAC measured at
= ( V
= The measured voltage difference between
FS
the given input code
two adjacent codes
– V
OUT
LSB = 4.095V/4095 = 1mV
LSB = 2.5V/4095 = 0.610mV
OUT
OS
– V
)/(2
– LSB)/LSB
OS
LTC1454/LTC1454L
n
– (V
– 1) = (V
FS
– V
FS
OS
– V
)(Code/4095)]/LSB
OS
)/4095
7