LTC2629IGN#TRPBF Linear Technology, LTC2629IGN#TRPBF Datasheet - Page 14

• Manufacturer Part Number: LTC2629IGN#TRPBF
• Description: IC DAC 12BIT R-R QUAD 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2629IGN#TRPBF

• Settling Time: 7µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 750µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2609/LTC2619/LTC2629
operation
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero-scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619-1/LTC2629-1 set the voltage outputs to mid-scale
when power is first applied.
For some applications, downstream circuits are active dur-
ing DAC power-up and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2609/LTC2619/
LTC2629 contain circuitry to reduce the power-on glitch;
furthermore, the glitch amplitude can be made arbitrarily
small by reducing the ramp rate of the power supply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
during power-on. See Power-On Reset Glitch in the Typical
Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REFx ≤ V
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
in transition. The REFx pins can be clamped to stay below
the maximum voltage by using Schottky diodes as shown
in Figure 2, thereby easing sequencing constraints.
Transfer Function
The digital-to-analog transfer function is:

Figure 2. Use of Schottky Diodes for Power Supply Sequencing
V
OUT IDEAL
(
)
LTC2609/
LTC2619/
LTC2629
=



2
k
REFD
REFA
REFB
REFC
N
V
CC



[
16
3
6
12
15
REFx REFLO
2609 F02
–
V
CC
CC
+ 0.3V (see Absolute
]
REFD
REFA
REFB
REFC
+
CC
REFLO
(Pin 16) is
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
using the standard 2-wire I
(Figure 1) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply and
can be obtained from the I
operating in the fast mode, an active pull-up will be necessary
if the bus capacitance is greater than 200pF. The V
should not be removed from the LTC2609/LTC2619/LTC2629
when the I
through the internal ESD protection diodes.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629. The LTC2609/LTC2619/LTC2629 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
2
2
C device.
C bus is active to avoid loading the I
2
2
C interface. The Timing Diagram
C specifications. For an I
2
C bus lines
CC
26091929fb
2
power
C bus