LTC1596-1ACSW Linear Technology, LTC1596-1ACSW Datasheet - Page 6

• Manufacturer Part Number: LTC1596-1ACSW
• Description: IC D/A CONV 16BIT MLTPLYNG16SOIC
• Manufacturer: Linear Technology

Specifications of LTC1596-1ACSW

• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN
LTC1595/LTC1596/LTC1596-1
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1595
V
R
of the current to voltage converter op amp.
OUT1 (Pin 3): Current Output Pin. Tie to inverting input of
current to voltage converter op amp.
GND (Pin 4): Ground Pin.
LD (Pin 5): The Serial Interface Load Control Input. When
LD is pulled low, data is loaded from the shift register into
the DAC register, updating the DAC output.
SRI (Pin 6): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded MSB first.
CLK (Pin 7): The Serial Interface Clock Input.
V
Requires a bypass capacitor to ground.
LTC1596/LTC1596-1
OUT1 (Pin 1): True Current Output Pin. Tie to inverting
input of current to voltage converter op amp.
OUT2 (Pin 2): Complement Current Output Pin. Tie to
analog ground.
AGND (Pin 3): Analog Ground Pin.
6
REF
DD
FB
U
(Pin 2): Feedback Resistor. Normally tied to the output
(Pin 8): The Positive Supply Input. 4.5V V
(Pin 1): Reference Input.
FUNCTIONS
U
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
Supply Current
vs Logic Input Voltage
U
V
DD
= 5V
1
W
INPUT VOLTAGE (V)
2
U
3
4
1595/96 G10
DD
5
5.5V.
STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial
Interface Clock Inputs. STB1, STB2 and STB4 are rising
edge triggered inputs. STB3 is a falling edge triggered
input (see Truth Tables).
LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs.
When LD1 and LD2 are pulled low, data is loaded from the
shift register into the DAC register, updating the DAC
output (see Truth Tables).
SRO (Pin 6): The Output of the Shift Register. Becomes
valid on the active edge of the serial clock.
SRI (Pin 7): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the active edge of the
serial clock. Data is loaded MSB first.
DGND (Pin 12): Digital Ground Pin.
CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero
scale when pulled low on LTC1596. Clears DAC to midscale
when pulled low on LTC1596-1. This pin should be tied to
V
V
5.5V. Requires a bypass capacitor to ground.
V
R
output of the current to voltage converter op amp.
DD
DD
REF
FB
for normal operation.
(Pin 14): The Positive Supply Input. 4.5V
(Pin 16): Feedback Resistor. Normally tied to the
(Pin 15): Reference Input.
3.0
2.5
2.0
1.5
1.0
0.5
0
0
Logic Threshold
vs Supply Voltage
1
2
SUPPLY VOLTAGE (V)
3
4
5
6
7
8
1595/96 G11
9
10
V
DD