CS4353-CNZR Cirrus Logic Inc, CS4353-CNZR Datasheet - Page 19

• Manufacturer Part Number: CS4353-CNZR
• Description: IC DAC STER 106DB 2VRMS 24-QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS4353-CNZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 152mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• For Use With: 598-1519 - BOARD EVAL FOR CS4353 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

DS803F1
4.9
4.9.1
4.9.2
Recommended Power-up and Power-down Sequences
4.9.1.1
Follow the power-up sequence below if the external RESET pin is used:
4.9.1.2
Follow the power-up sequence below if the internal power-on reset is used:
4.9.2.1
Follow the power-down sequence below if the external RESET pin is used:
4.9.2.2
Follow the power-down sequence below if the internal power-on reset is used:
Power-up Sequences
1. Hold RESET low while the power supplies are turned on.
2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as
4. After the power supplies, configuration pins, and clock signals are stable, bring RESET high. The
1. Hold RESET high (connected to VL) while the power supplies are turned on. The power-on reset
2. Set the I²S/LJ, 1_2VRMS, and DEM configuration pins to the desired state.
3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and
Power-down Sequences
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
2. Bring RESET low.
3. Remove the power supply voltages.
1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples.
2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin.
3. Remove the power supply voltages.
Note:
MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may
occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal
is removed during normal operation; see
discussed in
device will initiate the power-up sequence seen in
will be output from AOUTx within 50 ms after RESET is set high.
circuitry will function as described in
SCLK signals to progress from the ‘Power-Down State’ in the power-up sequence seen in
The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid
clocks are applied.
A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum
External RESET Power-up Sequence
Internal Power-on Reset Power-up Sequence
External RESET Power-down Sequence
Internal Power-on Reset Power-down Sequence
Section
4.3.
Section
“Switching Specifications - Serial Audio Interface” on page
4.7.
Figure
9. The sequence will complete and audio
CS4353
Figure
9.
9.
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