AD5300BRT-500RL7 Analog Devices Inc, AD5300BRT-500RL7 Datasheet - Page 4

• Manufacturer Part Number: AD5300BRT-500RL7
• Description: IC DAC 8BIT R-R 2.7-5.5V SOT23-6
• Manufacturer: Analog Devices Inc

Specifications of AD5300BRT-500RL7

• Rohs Status: RoHS non-compliant
• Settling Time: 4µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.4mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Number Of Channels: 1
• Resolution: 8b
• Conversion Rate: 250KSPS
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 6
• Package Type: SOT-23
• Lead Free Status / Rohs Status: Not Compliant

AD5300
SOT-23 MSOP
Pin No. Pin No. Mnemonic
1
2
3
4
5
6
NC
4
8
1
7
6
5
2, 3
V
GND
V
DIN
SCLK
SYNC
NC
OUT
DD
Function
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V
to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates up to 30 MHz.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the
input data. When SYNC goes low, it enables the input shift register and data is transferred in on the
falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless
SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the DAC.
No Connect.
V
GND
V
OUT
DD
1
2
3
(Not to Scale)
SOT-23
TOP VIEW
AD5300
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
6
5
4
SYNC
SCLK
DIN
–4–
V
V
OUT
NC
NC
DD
NC = NO CONNECT
1
2
3
4
(Not to Scale)
MSOP
TOP VIEW
AD5300
8
7
6
5
GND
DIN
SCLK
SYNC
DD
should be decoupled
REV.
D