AD9742ARURL7 Analog Devices Inc, AD9742ARURL7 Datasheet - Page 12

• Manufacturer Part Number: AD9742ARURL7
• Description: IC DAC 12BIT 210MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9742ARURL7

• Rohs Status: RoHS non-compliant
• Settling Time: 11ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 145mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD9742ACP-PCBZ - BOARD EVAL FOR AD9742ACP

AD9742
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9742. The
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16th of an MSB current source. The remaining LSBs
are binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC’s high output impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differ-
ential current switches. The switches are based on the architec-
ture that was pioneered in the AD9764 family, with further
refinements to reduce distortion contributed by the switching
transient. This switch architecture also reduces various timing
errors and provides matching complementary drive signals to
the inputs of the differential current switches.
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 210 MSPS, con-
sists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
pin. The external resistor, in combination with both the refer-
ence control amplifier and voltage reference ,V
reference current, I
current sources with the proper scaling factor. The full-scale
current, I
OUTFS
OUTFS
, is 32 times I
). The array is divided into 31 equal currents that
SET
REF
, connected to the full-scale adjust (FS ADJ)
, which is replicated to the segmented
REF
.
REFIO
, sets the
Rev. B | Page 12 of 32
REFERENCE OPERATION
The AD9742 contains an internal 1.2 V band gap reference. The
internal reference can be disabled by raising REFLO to AVDD.
It can also be easily overridden by an external reference with no
effect on performance. REFIO serves as either an input or an
output depending on whether the internal or an external refer-
ence is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1 µF capacitor and connect
REFLO to ACOM via a resistance less than 5 Ω. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is shown in Figure 23.
An external reference can be applied to REFIO, as shown in
Figure 24. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
ADDITIONAL
EXTERNAL
AVDD
LOAD
REF
REF BUFFER
EXTERNAL
OPTIONAL
R
SET
Figure 24. External Reference Configuration
Figure 23. Internal Reference Configuration
V
V
I
REFIO
REF
REFIO
0.1µF
=
2kΩ
/R
SET
REFIO
FS ADJ
REFIO
FS ADJ
1.2V REF
AD9742
AD9742
1.2V REF
REFLO
REFLO
150pF
150pF
REFERENCE
CONTROL
AMPLIFIER
CURRENT
SOURCE
ARRAY
CURRENT
SOURCE
3.3V
ARRAY
3.3V
AVDD
AVDD