AD5420AREZ Analog Devices Inc, AD5420AREZ Datasheet - Page 17

• Manufacturer Part Number: AD5420AREZ
• Description: IC DAC 16BIT 1CH SER 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5420AREZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
• Settling Time: 10µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 950mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 16bit
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where N is the total number of AD5410/AD5420 devices in the
chain. When the serial transfer to all devices is complete,
LATCH is taken high. This latches the input data in each device
in the daisy chain. The serial clock can be a continuous or a
gated clock.
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.
Table 9. Input Shift Register Contents for a Read Operation
MSB
DB23
0
1
X = don’t care.
DB22
0
CONTROLLER
SERIAL CLOCK
CONTROL OUT
Figure 39. Daisy Chaining the AD5410/AD5420
DATA IN
DATA OUT
*ADDITIONAL PINS OMITTED FOR CLARITY.
DB21
0
DB20
0
DB19
0
SDIN
SCLK
LATCH
SCLK
LATCH
SCLK
LATCH
AD5410/
AD5420*
AD5410/
AD5420*
AD5410/
AD5420*
DB18
0
SDIN
SDIN
SDO
SDO
SDO
DB17
1
Rev. B | Page 17 of 28
DB16
0
Readback Operation
Readback mode is invoked by setting the address byte and read
address as shown in Table 9 and Table 8 when writing to the
input shift register. The next write to the AD5410/AD5420
should be a NOP command, which clocks out the data from the
previously addressed register, as shown in Figure 3. By default,
the SDO pin is disabled. After having addressed the AD5410/
AD5420 for a read operation, a rising edge on LATCH enables
the SDO pin in anticipation of data being clocked out. After the
data has been clocked out on SDO, a rising edge on LATCH
disables (tristate) the SDO pin once again. To read back the
data register, for example, the following sequence should be
implemented:
1.
2.
Table 8. Read Address Decoding
Read Address
00
01
10
Write 0x020001 to the AD5410/AD5420 input shift
register. This configures the part for read mode with the
data register selected.
Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the data register is clocked
out on the SDO line.
DB15 to DB2
X
1
Function
Read status register
Read data register
Read control register
AD5410/AD5420
DB1
Read address
DB0
LSB