AD5555CRU Analog Devices Inc, AD5555CRU Datasheet - Page 10

• Manufacturer Part Number: AD5555CRU
• Description: IC DAC 14BIT DUAL SRL IN 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5555CRU

• Rohs Status: RoHS non-compliant
• Settling Time: 500ns
• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP

AD5545/AD5555
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire ( CS , SDI, CLK)
serial data interface for single channel update operation. With
Table 7 as an example (AD5545), users can tie LDAC low and
RS high, then pull CS low for an 18-bit duration. New serial
data is then clocked into the serial-input register in an 18-bit
data-word format with the MSB bit loaded first.
the truth table for the AD5555. Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK.
For the AD5545, only the last 18-bits clocked into the serial
register are interrogated when the
transferring the serial register data to the DAC register and
updating the output. If the applied microcontroller outputs
serial data in different lengths than the AD5545, such as 8-bit
bytes, three right justified data bytes can be written to the
AD5545. The AD5545 ignores the six MSB and recognizes the
18 LSB as valid data. After loading the serial register, the rising
edge of CS transfers the serial register data to the DAC register
and updates the output; during the CS strobe, the CLK should
not be toggled.
If users want to program each channel separately but update them
simultaneously, program LDAC and RS high initially, then pull
CS low for an 18-bit duration and program DAC A with the
proper address and data bits. CS is then pulled high to latch data
to the DAC A register. At this time, the output is not updated. To
Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
Bit Position
Data Word
1
Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
Bit Position
Data Word
1
Table 6. Address Decode
A1
0
0
1
1
Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
MSB
B17
A1
MSB
B15
A1
B16
A0
A0
0
1
0
1
B14
A0
B15
D15
CS pin is strobed high,
B13
D13
B14
D14
B12
D12
B13
D13
Table 8
DAC Decoded
None
DAC A
DAC B
DAC A and DAC B
B11
D11
B12
D12
defines
Rev. C | Page 10 of 20
B10
D10
B11
D11
B9
D9
B10
D10
load DAC B data, pull CS low for an 18-bit duration and program
DAC B with the proper address and data, then pull CS high to
latch data to the DAC B register. Finally, pull LDAC low and then
high to update both the DAC A and DAC B outputs
simultaneously.
Table 6 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with I
DAC with significant improved noise performance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and V
Figure 18.
B8
D8
B9
D9
B8
D8
B7
D7
Figure 18. Equivalent ESD Protection Circuits
B7
D7
B6
D6
OUT
B6
D6
A and I
V
B5
D5
DIGITAL
1
1
INPUTS
DD
DGND
5kΩ
B5
D5
OUT
B4
D4
B tied together, to act as one
02918- 0- 007
B4
D4
B3
D3
B3
D3
DD
B2
D2
as shown in
D2
B2
B1
D1
D1
B1
LSB
B0
D0
LSB
B0
D0