AD5325BRMZ Analog Devices Inc, AD5325BRMZ Datasheet - Page 16

• Manufacturer Part Number: AD5325BRMZ
• Description: IC DAC 12BIT 2WIRE I2C 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5325BRMZ

• Data Interface: I²C, Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 600µA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5305/AD5315/AD5325
SERIAL INTERFACE
The AD5305/AD5315/AD5325 are controlled via an I
compatible serial bus. The DACs are connected to this bus as
slave devices (that is, no clock is generated by the AD5305/
AD5315/AD5325 DACs). This interface is SMBus compatible
at V
The AD5305/AD5315/AD5325 have a 7-bit slave address. The
6 MSB are 000110 and the LSB is determined by the state of the
A0 pin. The facility to make hardwired changes to A0 allows the
user to use up to two of these devices on one bus. The 2-wire
serial bus protocol operates as follows:
1.
2.
3.
DD
The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
followed by an R/ W bit (this bit determines whether data is
read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a No
Acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the 10
10
< 3.6 V.
th
clock pulse to establish a stop condition.
MSB
MSB
MSB
PD1
PD1
PD1
PD0
PD0
PD0
th
clock pulse and then high during the
MOST SIGNIFICANT DATA BYTE
CLR
CLR
CLR
10-BIT AD5315
12-BIT AD5325
8-BIT AD5305
LDAC
LDAC
LDAC
th
clock pulse to establish a
D11
D7
D9
D10
D6
D8
Figure 32. Data Formats for Write and Readback
DATA BYTES (WRITE AND READBACK)
2
C
D5
D7
D9
LSB
LSB
LSB
Rev. G | Page 16 of 24
D4
D6
D8
MSB
MSB
MSB
D3
D5
D7
READ/WRITE SEQUENCE
In the case of the AD5305/AD5315/AD5325, all write access
sequences and most read sequences begin with the device
address (with R/ W = 0) followed by the pointer byte. This
pointer byte specifies the data format and determines which
DAC is being accessed in the subsequent read/write operation
(see Figure 31). In a write operation, the data follows
immediately. In a read operation, the address is resent with
R/ W = 1 and then the data is read back. However, it is also
possible to perform a read operation by sending only the
address with R/ W = 1. The previously loaded pointer settings
are then used for the readback operation. See Figure 32 for a
graphical explanation of the interface.
POINTER BYTE BITS
Table 6 explains the individual bits that make up the pointer byte.
Table 6. Individual Bits of the Pointer Byte
Bit
X
0
DACD
DACC
DACB
DACA
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for
this operation is shown in Figure 2. The two data bytes consist
of four control bits followed by 8, 10, or 12 bits of DAC data,
depending on the device type. The first two bits loaded are the
PD1 and PD0 bits that control the mode of operation of the device.
See the Power-Down Modes section for a complete description.
Bit 13 is CLR , Bit 12 is LDAC , and the remaining bits are left
justified DAC data bits, starting with the MSB. See Figure 32.
D2
D4
D6
MSB
X
LEAST SIGNIFICANT DATA BYTE
D5
Description
Don’t care bits.
Reserved bits. Must be set to 0.
[1] The following data bytes are for DAC D.
[1] The following data bytes are for DAC C.
[1] The following data bytes are for DAC B.
[1] The following data bytes are for DAC A.
D1
D3
X
10-BIT AD5315
8-BIT AD5305
12-BIT AD5325
D0
D2
D4
0
Figure 31. Pointer Byte
D1
D3
0
0
D0
D2
0
DACD
D1
DACC DACB DACA
0
0
LSB
LSB
LSB
D0
0
0
LSB