AD8842AR Analog Devices Inc, AD8842AR Datasheet - Page 2

• Manufacturer Part Number: AD8842AR
• Description: IC DAC 8BIT OCTAL MULT 24-SOIC
• Manufacturer: Analog Devices Inc
• Series: TrimDAC®r

Specifications of AD8842AR

• Rohs Status: RoHS non-compliant
• Settling Time: 2.9µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 135mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Number Of Channels: 8
• Resolution: 8b
• Conversion Rate: 500KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±5V
• Architecture: R-2R
• Power Supply Requirement: Dual
• Output Type: Voltage
• Integral Nonlinearity Error: ±1LSB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±4.75V
• Dual Supply Voltage (max): ±5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

AD8842–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H
VOLTAGE INPUTS—Applies to All Inputs V
DAC OUTPUTS—Applies to All Outputs V
DYNAMIC PERFORMANCE—Applies to All DACs
POWER SUPPLIES
DIGITAL INPUTS
DIGITAL OUTPUT
TIMING SPECIFICATIONS
NOTES
1
2
Specifications subject to change without notice.
Guaranteed by design, not subject to production test.
Calculated limit = 5 V
Resolution
Integral Nonlinearity Error
Differential Nonlinearity
Full-Scale Gain Error
Output Offset
Output Offset Drift
Input Voltage Range
Input Resistance
Input Capacitance
Voltage Range
Output Current
Capacitive Load
Full Power Gain Bandwidth
Slew Rate
Total Harmonic Distortion
Spot Noise Voltage
Output Settling Time
Channel-to-Channel Crosstalk
Digital Feedthrough
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Rejection
Power Supply Range
Logic High
Logic Low
Input Current
Input Capacitance
Input Coding
Logic High
Logic Low
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Preset Pulse Width
Clock Edge to Load Time
Load Edge to Next Clock Edge
Positive
Negative
1
(I
2
DD
1
+ I
SS
).
1
1
Symbol
N
INL
DNL
G
V
TCV
IVR
R
C
OVR
I
C
GBW
SR+
SR–
THD
e
t
C
Q
I
I
P
PSRR
PSR
V
V
I
C
V
V
t
t
t
t
t
t
t
t
OUT
S
DD
SS
L
CH
DS
DH
PD
LD
PR
CKLD
LDCK
N
DISS
BZE
IN
IH
IL
OH
OL
IN
L
T
IL
FSE
, t
OUT
BZ
CL
IN
x
x
(V
DD
Conditions
All Devices Monotonic
PR = 0, Sets D = 80
PR = 0, Sets D = 80
R
No Oscillation
V
Measured 10% to 90%
V
f
f = 1kHz, V
Measured Between Adjacent
Channels, f = 100 kHz
V
PR = 0 V
PR = 0 V
PR = 0 V, V
V
I
I
LPF
OH
OL
V
V
V
1 LSB Error Band, D = 00
= +5 V, V
L
IN
IN
IN
DD
OUT
OUT
OUT
= 10 k
x = 3 V
x = 4 V p-p, D = FF
x = 0 V, D = 0 to 255
= 1.6 mA
= –0.4 mA
, |V
= 80 kHz, R
x = +5.5 V
x = –5.5 V
< 1.5 LSB
SS
|
SS
IN
P
= –5 V, All V
, R
DD
–2–
= 0 V
L
L
= 5%
= 2 k , C
= 1 k
H
H
D = FF
H
IN
, f = 1 kHz,
10
x = +3 V, T
L
H
H
= 10 pF
to FF
to 00
H
H
A
= –40 C to +85 C, unless otherwise noted.)
Min
8
12
10
0.5
1.0
4.75
2.4
3.5
60
40
20
70
50
30
60
3
3
3
Offset Binary
Typ
2
5
5
19
9
500
50
1.0
1.8
0.01
78
2.9
5.4
72
5
10
9
95
0.0001
5.00
7
0.2
0.4
4
4
Max
25
14
13
135
0.01
5.25
0.8
0.4
80
1
1
10
Units
Bits
LSB
LSB
LSB
mV
V
k
pF
V
mA
pF
kHz
V/ s
V/ s
%
nV/ Hz
dB
nV-s
mA
mA
mW
%/%
V
V
V
pF
V
V
ns
ns
ns
ns
ns
ns
ns
ns
V/ C
s
s
A
REV. 0