AD420ARZ-32 Analog Devices Inc, AD420ARZ-32 Datasheet - Page 11

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AD420ARZ-32

Manufacturer Part Number
AD420ARZ-32
Description
IC DAC SRL 16BIT 24-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD420ARZ-32

Data Interface
Serial
Settling Time
2.5µs
Number Of Bits
16
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
176mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Resolution (bits)
16bit
Sampling Rate
400SPS
Input Channel Type
Serial
Supply Current
4.2mA
Digital Ic Case Style
SOIC
No. Of Pins
24
Number Of Channels
1
Resolution
16b
Conversion Rate
0.4KSPS
Interface Type
SERIAL 3W SPI UW
Single Supply Voltage (typ)
15/18/24V
Dual Supply Voltage (typ)
Not RequiredV
Architecture
Delta-Sigma
Power Supply Requirement
Single
Output Type
Current/Voltage
Integral Nonlinearity Error
±0.012LSB
Single Supply Voltage (min)
12V
Single Supply Voltage (max)
32V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
24
Package Type
SOIC W
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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THREE-WIRE INTERFACE
Figure 9 shows the AD420 connected in the 3-wire interface
mode. The AD420 data input block contains a serial input shift
register and a parallel latch. The contents of the shift register
are controlled by the DATA IN signal and the rising edges of the
CLOCK. Upon request of the LATCH pin the DAC and internal
latch are updated from the shift register parallel outputs. The
CLOCK should remain inactive while the DAC is updated.
Refer to the timing requirements for 3-wire interface.
DATA IN
USING MULTIPLE DACS WITH FAULT DETECT
The 3-wire interface mode can utilize the serial DATA OUT for
easy interface to multiple DACs. To program the two AD420s in
Figure 9, 32 data bits are required. The first 16 bits are clocked
into the input shift register of DAC1. The next 16 bits
transmitted pass the first 16 bits from the DATA OUT pin of
DAC1 to the input register of DAC2. The input shift registers of
the two DACs operate as a single 32-bit shift register, with the
leading 16 bits representing information for DAC2 and the
trailing 16 bits serving for DAC1. Each DAC is then updated
upon request of the LATCH pin. The daisy-chain can be
extended to as many DACs as required.
CLOCK
LATCH
Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect
FAULT
DETECT
LATCH
CLOCK
DATA
IN
GND
AD420
DAC1
DATA
OUT
I
V
OUT
CC
V
CC
R
LOAD
10kΩ
FAULT DETECT
FAULT
DETECT
LATCH
CLOCK
DATA
IN
GND
V
LL
AD420
DAC2
DATA
OUT
I
V
OUT
CC
V
CC
R
LOAD
Rev. H | Page 11 of 16
ASYNCHRONOUS INTERFACE USING
OPTOCOUPLERS
The AD420 connected in asynchronous interface mode with
optocouplers is shown in Figure 10. Asynchronous operation
minimizes the number of control signals required for isolation
of the digital system from the control loop. The resistor connected
between the LATCH pin and V
mode. For operation with V
resistor; from 18 V to 32 V, use 100 kΩ.
Asynchronous mode requires that the clock run at 16 times the
data bit rate, therefore, to operate at the maximum input data rate
of 150 kBPS, an input clock of 2.4 MHz is required. The actual
data rate achieved may be limited by the type of optocouplers
chosen. The number of control signals can be further reduced
by creating the appropriate clock signal on the current loop
side of the isolation barrier. If optocouplers with relatively slow
rise and fall times are used, Schmitt triggers may be required on
the digital inputs to prevent erroneous data being presented to
the DAC.
CLOCK
DATA
Figure 10. Asynchronous Interface Using Optocouplers
GALVANIC
BARRIER
+5V
ISOLATION
100kΩ
CC
below 18 V use a 50 kΩ pull-up
CC
+24V
is required to activate this
23
11
7
2
8
9
V
LATCH
V
CLOCK
DATA IN
GND
CC
LL
AD420
AD420

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