MT4HTF6464AY-800E1 Micron Technology Inc, MT4HTF6464AY-800E1 Datasheet - Page 16
![](/photos/31/34/313449/240pin_udimm_sml.jpg)
MT4HTF6464AY-800E1
Manufacturer Part Number
MT4HTF6464AY-800E1
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT4HTF6464AY-800E1.pdf
(19 pages)
Specifications of MT4HTF6464AY-800E1
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
1Gb
Access Time (max)
40ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.28A
Number Of Elements
4
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / Rohs Status
Compliant
Table 13: DDR2 I
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (32 Meg x 16) com-
ponent data sheet
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
RP =
t
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
DD
); CKE is HIGH, S# is HIGH between valid commands;
RP (I
Specifications and Conditions (Die Revision E) – 512MB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
); CKE is HIGH, S# is HIGH between valid com-
t
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
), AL = 0;
DD
DD
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
16
Fast PDN exit
MR[12] = 0
Slow PDN ex-
it MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
-80E/
-800
1260
1280
1120
600
700
300
320
160
340
28
40
28
1080
-667
© 2003 Micron Technology, Inc. All rights reserved.
540
520
260
280
120
300
800
880
28
40
28
I
DD
-53E
1000
Specifications
440
480
180
200
120
240
720
720
28
40
28
-40E
440
460
160
160
120
220
640
640
960
28
40
28
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA