STK15C88-S35I Cypress Semiconductor Corp, STK15C88-S35I Datasheet - Page 7

• Manufacturer Part Number: STK15C88-S35I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK15C88-S35I

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 80mA
• Lead Free Status / Rohs Status: Not Compliant

The STK15C88 is a versatile memory chip that pro-
vides several modes of operation. The STK15C88
can operate as a standard 32K x 8
32K x 8
mation can be copied, or from which the
be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK15C88 is a high speed memory
and so must have a high frequency bypass capaci-
tor of approximately 0.1 F connected between DUT
V
as possible. As with all high speed CMOS ICs, nor-
mal careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK15C88 performs a
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E or G, the outputs will be valid at t
at t
data outputs will repeatedly respond to address
changes within the t
need for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
August 1998
CC
WRITE
GLQV
and V
WRITE
, whichever is later (
EEPROM
cycle is performed whenever E and W are
SS
0-14
, using leads and traces that are as short
WRITE
WRITE
determines which of the 32,768 data
cycle to avoid data bus contention on
AVQV
WRITE
shadow to which the
.
(
READ CYCLE
cycle and must remain stable
AVQV
or t
access time without the
READ
DVEH
READ CYCLE
WLQZ
before the end of an
DVWH
after W goes low.
cycle whenever E
#1). If the
READ
DEVICE OPERATION
SRAM
before the end
0-7
SRAM
will be writ-
SRAM
is initiated
#2). The
. It has a
READ
ELQV
infor-
can
or
is
5-41
SOFTWARE NONVOLATILE STORE
The STK15C88 software
executing sequential
address locations. During the
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of reads from specific
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
The software sequence is clocked with E controlled
reads.
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
SOFTWARE NONVOLATILE RECALL
A software
of
ware
the following sequence of
performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
READ
STORE
sequence must be performed:
and
operations in a manner similar to the soft-
WRITE
WRITE
RECALL
initiation. To initiate the
STORE
STORE
cycles be used in the sequence,
operation.
SRAM
READ
cycle is initiated with a sequence
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
cycle will commence and the
READ
STORE
or
STORE
will again be activated for
STORE
or
RECALL
READ
cycles from six specific
WRITE
STORE
STORE
initiation, it is impor-
STORE
cycle, the following
operations must be
cycle is initiated by
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
will take place.
SRAM
accesses inter-
STK15C88
cycle an erase
RECALL
cycle time has
cycle is initi-
READ
data into
cycles
cycle,