TFDU6102 Vishay, TFDU6102 Datasheet - Page 8

• Manufacturer Part Number: TFDU6102
• Manufacturer: Vishay
• Type: TX/RXr

Specifications of TFDU6102

• Data Rate: 0.004kbps
• Peak Wavelength: 900nm
• Angle Of Half Sensitivity: 48°
• Pulse Width: 2.1us
• Communication Distance: 100
• Led Supply Voltage: -0.5 to 6.5V
• Fall Time: 40ns
• Rise Time: 40ns
• Dimensions: 9.7x4.7x4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 8
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

I/O and Software
In the description, already different I/Os are men-
tioned. Different combinations are tested and the
function verified with the special drivers available
from the I/O suppliers. In special cases refer to the I/
O manual, the Vishay application notes, or contact
directly Vishay Sales, Marketing or Application.
Mode Switching
The TFDU6102 is in the SIR mode after power on as
a default mode, therefore the FIR data transfer rate
has to be set by a programming sequence using the
TXD and SD inputs as described below or selected by
setting the Mode Pin. The Mode Pin can be used to
statically set the mode (Mode Pin: LOW: SIR, HIGH:
0.576 Mbit/s to 4.0 Mbit/s). If not used or in standby
mode, the mode input should float or should not be
loaded with more than 50 pF. The low frequency
mode covers speeds up to 115.2 kbit/s. Signals with
higher data rates should be detected in the high fre-
quency mode. Lower frequency data can also be
received in the high frequency mode but with reduced
sensitivity.
To switch the transceivers from low frequency mode
to the high frequency mode and vice versa, the pro-
gramming sequences described below are required.
Setting to the High Bandwidth Mode
(0.576 Mbit/s to 4.0 Mbit/s)
1. Set SD input to logic "HIGH".
2. Set TXD input to logic "HIGH". Wait t
3. Set SD to logic "LOW" (this negative edge latches
state of TXD, which determines speed setting).
4. After waiting t
"LOW". The hold time of TXD is limited by the maxi-
mum allowed pulse length.
Table 2.
Truth table
Document Number 82550
Rev. 1.7, 21-Aug-06
high
low
SD
high > 80 µs
h
≥ 200 ns TXD can be set to logic
TXD
high
low
low
low
x
Inputs
Optical input Irradiance mW/m
s
< Max. irradiance Ee
> Max. irradiance Ee
> Min. irradianceEe
≥ 200 ns.
< 4
x
x
x
After that TXD is enabled as normal TXD input and the
transceiver is set for the high bandwidth (576 kbit/s to
4 Mbit/s) mode.
Setting to the Lower Bandwidth Mode
(2.4 kbit/s to 115.2 kbit/s)
1. Set SD input to logic "HIGH".
2. Set TXD input to logic "LOW". Wait t
3. Set SD to logic "LOW" (this negative edge latches
state of TXD, which determines speed setting).
4. TXD must be held for t
After that TXD is enabled as normal TXD input and the
transceiver is set for the lower bandwidth (9.6 kbit/s to
115.2 kbit/s) mode.
SD
TXD
2
Figure 2. Mode Switching Timing Diagram
50 %
(500 kΩ) to V
weakly pulled
low (active)
low (active)
t
Vishay Semiconductors
s
RXD
high
high
h
x
≥ 200 ns.
50 %
Outputs
t
CC1
h
50 %
TFDU6102
s
Hig h : F IR
www.vishay.com
Low : SIR
≥ 200 ns.
Transmitter
I
0
0
0
0
0
e
14873
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