ADMCF328BRZ Analog Devices Inc, ADMCF328BRZ Datasheet
ADMCF328BRZ
Specifications of ADMCF328BRZ
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ADMCF328BRZ Summary of contents
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TARGET APPLICATIONS Washing Machines, Refrigerator Compressors, Fans, Pumps, Industrial Variable Speed Drives MOTOR TYPES Permanent Magnet Synchronous Motors (PMSM) Brushless DC Motors (BDCM) FEATURES 20 MIPS Fixed-Point DSP Core Single Cycle Instruction Execution (50 ns) ADSP-21xx Family Code Compatible ...
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ADMCF328–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 2 Zero Offset Channel-to-Channel Comparator Match Comparator Delay 2 ADC High Level Input Current 2 ADC Low Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double ...
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VOLTAGE REFERENCE Parameter Voltage Level (V ) REF Output Voltage Drift Specifications subject to change without notice. I Amplifier–TRIP SENSE Parameter I Gain SENSE I Current SENSE I Input Offset Voltage SENSE Trip Voltage (V ) TRIP Specifications subject to ...
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ADMCF328 TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMCF328 uses an input clock with a CK CKIN frequency equal to half the instruction rate MHz input clock (which is equivalent to ...
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Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to ...
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ADMCF328 ABSOLUTE MAXIMUM RATINGS* Supply Voltage ( –0 +7 Input Voltage . . . . . . ...
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GENERAL DESCRIPTION The ADMCF328 is a low cost, single-chip DSP-based control- ler, suitable for permanent magnet synchronous motors, and brushless dc motors. The ADMCF328 integrates a 20 MIPS, fixed-point DSP core with a complete set of motor control and system ...
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ADMCF328 DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMCF328, which is based on the fixed-point ADSP-2171. The flexible architecture and comprehensive instruction set of the ADSP-2171 allow the processor to ...
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Serial Port The ADMCF328 incorporates a complete synchronous serial port (SPORT1) for serial communication and multiprocessor com- munication. The following is a brief list of capabilities of the ADMCF328 SPORT1. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for ...
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ADMCF328 FLASH MEMORY SUBSYSTEM The ADMCF328 has 4K × 24-bit of user-programmable, non- volatile flash memory. A flash programming utility is provided with the development tools, which performs the basic device programming operations: erase, program, and verify. The flash memory ...
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V RST RST RESET Figure 5. Power-On Reset Operation The ADMCF328 reset sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the MSTAT register and performs a full reset of all of ...
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ADMCF328 A functional block diagram of the PWM controller is shown in Figure 6. The generation of the six output PWM signals on pins controlled by four important blocks: • The three-phase PWM timing unit, which ...
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PWM Switching Dead Time: PWMDT Register The second important PWM block parameter that must be initialized is the switching dead time. This is a short delay time introduced between turning off one PWM signal (for example AH) and turning on ...
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ADMCF328 PWMCHA PWMCHA AH 2 PWMDT AL PWMSYNC SYSSTAT (3) PWMTM Figure 7. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode Each switching edge is moved by an equal amount (PWMDT × preserve the ...
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PWM signals each half period ( for the full period double update mode, improved resolution is possible since different values of the duty cycle ...
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ADMCF328 PWMCHA PWMCHA = PWMCHB = PWMCHB AH 2 PWMDT PWMTM Figure 9. An example of PWM signals suitable for ECM control. PWMCHA = PWMCHB, BH/BL are a crossover pair. AL, BH, CH, and CL ...
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Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF328 16-BIT PWM TIMER Parameter Counter Resolution Edge Resolution (Single Update Mode) Edge Resolution (Double Update Mode) Programmable Dead Time Range Programmable Dead Time Increments Programmable Pulse Deletion Range Programmable Pulse ...
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ADMCF328 VIL t VIL T –T PWM CRST PWMSYNC COMPARATOR OUTPUT Figure 12. Analog Input Block Operation The ADC system consists of four comparators and a single timer, which may be clocked at either the DSP rate ...
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ADC Reference Ramp Calibration The peak of the ADC ramp voltage should be as close as possible to 3 achieve the optimum ADC resolution and signal range. When the current source is in the Default State, the peak ...
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ADMCF328 UPPER DIODE CONDUCTION LOWER TRANSISTOR LOWER TRANSISTOR V WINDING CONDUCTION CONDUCTION I WINDING I BUS PWMSYNC Figure 17. Bus Current Signals The auxiliary PWM system of the ADMCF328 can operate in two different modes: independent mode or offset mode. ...
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Table VIII. Fundamental Characteristics of Auxiliary PWM Timer of ADMCF328 AUXILIARY PWM TIMERS Parameter Resolution PWM Frequency WATCHDOG TIMER The ADMCF328 incorporates a watchdog timer that can per- form a full reset of the DSP and motor control peripherals in ...
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ADMCF328 The functionality of the PIO6/CLKOUT, PIO7/AUX1, and PIO8/AUX0 pins may be selected on a pin-by-pin basis as desired. PIO Registers The configuration of all registers of the PIO system is shown at the end of the data sheet. INTERRUPT ...
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SYSTEM CONTROLLER The system controller block of the ADMCF328 performs the following functions: 1. Manages the interface and data transfer between the DSP core and the motor control peripherals. 2. Handles interrupts generated by the motor control peripherals and generates ...
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ADMCF328 Address (HEX) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PIODIR0 0x2005 PIODATA0 0x2006 PIOINTEN0 0x2007 PIOFLAG0 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 ...
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Address Name 0x3FFF SYSCNTL 0x3FFE MEMWAIT 0x3FFD TPERIOD 0x3FFC TCOUNT 0x3FFB TSCALE 0x3FFA . . . F3 0x3FF2 SPORT1_CTRL_REG 0x3FF1 SPORT1_SCLKDIV 0x3FF0 SPORT1_RFSDIV 0x3FEF SPORT1_AUTOBUF_CTRL REV. A Table XI. DSP Core Registers Bits [ [15 . ...
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ADMCF328 BOOT–FROM–FLASH–CODE RESERVED ALWAYS READ 0 Figure 21. Configuration of Flash Memory Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should ...
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A CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown; if ...
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ADMCF328 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING ...
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ADMCF328 Figure 25. Configuration of Additional PIO Registers Default bit values are shown value ...
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Default bit values are shown value ...
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ADMCF328 Figure 27. Configuration of Additional AUX Registers Default bit values are shown value is shown, the bit field is undefined ...
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OFFSET MODE AUXILIARY 1 = INDEPENDENT MODE PWM SELECT ADC 0 = CLKIN RATE COUNTER 1 = CLKOUT RATE SELECT 1ST HALF OF PWM ...
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ADMCF328 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2 DISABLE (MASK) ...
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DISABLED SPORT1 ENABLE 1 = ENABLED NOTE THE ROM MONITOR WRITES 0x8000 TO THIS REGISTER REV. A SYSCNTL (R/ ...
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ADMCF328 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AE PIN 1 6.35 (0.2500) ...