EVAL-ADN2816EB Analog Devices Inc, EVAL-ADN2816EB Datasheet - Page 10

• Manufacturer Part Number: EVAL-ADN2816EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2816EB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADN2816
Table 6. Internal Register Map
Reg Name
FREQ0
FREQ1
FREQ2
RATE
MISC
CTRLA
CTRLB
CTRLC
1
Table 7. Miscellaneous Register, MISC
D7
x
Table 8. Control Register, CTRLA
F
D7
0
0
1
1
1
Table 9. Control Register, CTRLB
Config LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
D7
Set to 0
All writeable registers default to 0x00.
Where DIV_F
REF
Range
D6
x
D6
0
1
0
1
REF
D5
x
D6
Set to 0
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
80 MHz to 160 MHz
is the divided down reference referred to the 10 MHz to 20 MHz band (see the R
R/W
R
R
R
R
R
W
W
W
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
Address
0x0
0x1
0x2
0x3
0x4
0x8
0x9
0x11
D5
Set to 0
Reset MISC[4]
D6
Write a 1 followed by
0 to reset MISC[4]
1
D7
MSB
MSB
0
x
Config
LOL
0
1
D4
Set to 0
F
COARSE_RD[8] MSB
REF
Data Rate/Div_F
D5
0
0
0
1
Range
D6
MSB
x
Reset
MISC[4]
0
D4
0
0
0
0
LOL Status
D3
0 = Locked
1 = Acquiring
D3
Set to 0
n
D3
0
0
1
0
D5
x
System
Reset
0
System Reset
D5
Write a 1 followed by
0 to reset ADN2816
REF
D2
0
1
0
0
Ratio
Rev. A | Page 10 of 24
D2
Set to 0
Data Rate/DIV_F
Data Rate Measurement Complete
D2
0 = Measuring data rate
1 = Measurement complete
D4
Static
LOL
0
0
1
2
4
2
256
Coarse Data Rate Readback
n
Measure Data Rate
D1
Set to 1 to measure data rate
D3
LOL
Status
Reset
MISC[2]
0
SQUELCH Mode
D1
0 = SQUELCH CLK and DATA
1 = SQUELCH CLK or DATA
D4
Set to 0
REF
eference Clock (Optional)
Ratio
D2
Data Rate
Measure
Complete
0
0
Reset MISC[2]
D3
Write a 1 followed by
0 to reset MISC[2]
D1
x
Measure Data Rate
0
SQUELCH Mode
section).
D1
x
Lock to Reference
D0
1 = Lock to reference clock
0 = Lock to input data
Output Boost
D0
0 = Default output swing
1 = Boost output swing
Coarse Rate Readback LSB
D0
COARSE_RD[0]
COARSE_RD[1]
D2
Set to 0
D0
LSB
LSB
LSB
COARSE_RD[0] LSB
Lock to Reference
0
Output Boost
D1
Set to 0
D0
Set to 0