AD7237AAR Analog Devices Inc, AD7237AAR Datasheet - Page 2

• Manufacturer Part Number: AD7237AAR
• Description: IC DAC 12BIT W/AMP W/BUFF 24SOIC
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD7237AAR

• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SOIC (7.5mm Width)
• Resolution (bits): 12bit
• No. Of Pins: 24
• Update Rate: 0.125MSPS
• Supply Voltage Min: 12V
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 15V
• No. Of Bits: 12 Bit
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

R
Parameter
STATIC PERFORMANCE
REFERENCE OUTPUT
REFERENCE INPUT
DIGITAL INPUTS
ANALOG OUTPUTS
AC CHARACTERISTICS
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
AD7237A/AD7247A–SPECIFICATIONS
Power Supply tolerance is 10% for A version and 5% for B and T versions.
Temperature ranges are as follows: A, B Versions, –40 C to +85 C; T Version, –55 C to +125 C.
See Terminology.
With appropriate power supply tolerances.
Measured with respect to REF IN and includes unipolar/bipolar offset error.
Sample tested @ +25 C to ensure compliance.
0 V to +10 V range is only available with V
L
Resolution
Relative Accuracy
Differential Nonlinearity
Unipolar Offset Error
Bipolar Zero Error
Full-Scale Error
Full-Scale Mismatch
REF OUT
Reference Temperature
Reference Load Change
Reference Input Range
Input Current
Input High Voltage, V
Input Low Voltage, V
Input Current
Input Capacitance
Output Range Resistors
Output Voltage Ranges
Output Voltage Ranges
DC Output Impedance
Voltage Output Settling Time
Digital-to-Analog Glitch
Digital Feedthrough
Digital Crosstalk
V
V
I
I
= 2 k , C
DD
SS
Coefficient
( REF OUT vs. I)
I
Positive Full-Scale Change
Negative Full-Scale Change 8
Impulse
DD
SS
IN
(Dual Supplies)
(Data Inputs)
3
L
= 100 pF. All specifications T
6
3, 5
3
3
6
3
3
5
3
INL
INH
7
7
3
6
A
12
4.97/5.03
–1
4.75/5.25
2.4
0.8
8
15/30
+5, +10
+5, +10, 5 +5, +10, 5 +5, +10, 5
0.5
8
30
10
30
+10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/max
–10.8/–16.5
15
5
1
0.9
3
6
5
1
25
5
10
2
DD
14.25 V.
MIN
to T
B
12
4.97/5.03
–1
4.75/5.25
2.4
0.8
8
15/30
+5, +10
0.5
8
8
30
10
30
–11.4/–15.75 –11.4/–15.75 V min/max
15
5
1/2
0.9
3
4
5
1
25
5
10
2
MAX
unless otherwise noted.)
T
12
4.95/5.05
–1
4.75/5.25
2.4
0.8
8
15/30
0.5
10
10
30
10
30
15
5
1/2
0.9
4
6
6
1
25
5
10
2
–2–
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB typ
V min/max
ppm/ C typ
mV max
V min/max
V min
V max
pF max
k min/max
V
nV secs typ DAC Latch Contents Toggled Between all 0s and all 1s
nV secs typ
nV secs typ
mA max
mA max
A max
A max
s max
s max
typ
(V
DGND = 0 V [AD7237A], GND = 0 V [AD7247A], REF IN = +5 V,
DD
= +12 V to +15 V,
5 V
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Test Conditions/Comments
Guaranteed Monotonic
V
V
1000 0000 0000
Reference Load Current Change (0-100 A)
V
Single Supply; (V
Dual Supply; (V
Settling Time to Within 1/2 LSB of Final Value
DAC Latch all 0s to all 1s. Typically 5 s
DAC Latch all 1s to all 0s. Typically 5 s
V
Output Unloaded. Typically 10 mA
Output Unloaded. Typically 3 mA
SS
SS
IN
SS
= 0 V or –12 V to –15 V
= –12 V to –15 V
= 0 V to V
= –12 V to –15 V
5%
1
DD
V
SS
SS
SS
= –12 V to –15 V
= 0 V or –12 V to –15 V,
= 0 V)
4
4
. DAC Latch Contents
.
4
. DAC Latch Contents All 0s
4
)
1
AGND =
REV. 0