IS41LV16257-35K ISSI, Integrated Silicon Solution Inc, IS41LV16257-35K Datasheet - Page 9

• Manufacturer Part Number: IS41LV16257-35K
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DRAMr

Specifications of IS41LV16257-35K

• Density: 4Mb
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 230mA
• Pin Count: 40
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

IS41C16257
IS41LV16257
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
2. V
3. In addition to meeting the transition rate specification, all input signals must transit between V
4. If
5. If
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
8. Assumes that t
9. If
10. Operation with the t
11. Operation within the t
12. Either t
13. t
14. t
15. Output parameter (I/O) is referenced to corresponding
16. During a READ cycle, if
17. Write command is defined as
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
19. The I/Os are in open during READ cycles once t
20. The first
21. The last
22. These parameters are referenced to
23. Last falling
24. Last rising
25. Last rising
26. Each
27. Last
28. I/Os controlled, regardless
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
DR004-1B
05/24/99
operation is assured. The eight
V
in a monotonic manner.
the amount that t
data output buffer,
is greater than the specified t
is greater than the specified t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
(MIN), t
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
to V
WRITE or READ-MODIFY-WRITE is not possible.
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
and
MODIFY-WRITE cycles.
OFF
WCS
IH
IL
CAS
CAS
CAS
(or between V
(MIN) and V
IH
, t
OE
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
) is indeterminate.
RWD
CAS
is LOW at the falling edge of
and
= V
CAS
RCH
AWD
is taken back to LOW after t
, t
CAS
CAS
IL
or t
to go LOW.
RAS
AWD
, data output may contain data from the last valid READ cycle.
CAS
CAS
must meet minimum pulse width.
CAS
t
AWD
RRH
RCD
RCD
edge to transition HIGH.
edge to transition LOW.
IL
and t
= V
RCD
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
edge to next cycle’s last rising
edge to first falling
IL
edge to first rising
(MIN) and t
must be satisfied for a READ cycle.
CAS
and V
RCD
IH
t
CWD
exceeds the value shown.
t
RCD
RAD
, data output is High-Z.
RCD
OE
(MAX) limit ensures that t
and
OE
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
(MAX). If t
(MAX) limit ensures that t
IH
(MAX).
is LOW then taken HIGH before
) and assume to be 1 ns for all inputs.
UCAS
held HIGH and
RAS
RCD
RAD
CWD
WE
RAS
(MAX) limit, access time is controlled exclusively by t
(MAX) limit, access time is controlled exclusively by t
must be pulsed for t
going low.
and
RCD
RAS
t
OEH
CWD
CAS
cycles wake-up should be repeated any time the t
CAS
CAS
LCAS
is greater than the maximum recommended value shown in this table, t
, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
is met.
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
leading edge in EARLY WRITE cycles and
edge.
edge.
WE
.
taken LOW after
OD
RAC
CAS
RCD
or t
(MAX) can be met. t
CP
(MAX) can be met. t
OFF
edge.
CAS
.
CAS
occur.
input, I/O0-I/O7 by
goes HIGH, I/O goes open. If
OD
CAS
and t
RAS
goes LOW result in a LATE WRITE (
OEH
RCD
RAD
refresh cycle (
met (
(MAX) is specified as a reference point only; if t
(MAX) is specified as a reference point only; if t
LCAS
OE
HIGH during WRITE cycle) in order to ensure
WE
and I/O8-I/O15 by
AA
CAC
REF
RAS
.
leading edge in LATE WRITE or READ-
.
refresh requirement is exceeded.
OE
-Only or CBR) before proper device
IH
is tied permanently LOW, a LATE
and V
CAS
IL
(or between V
and
UCAS
OE
OH
RAS
RAC
CAS
-controlled) cycle.
ISSI
.
or V
will increase by
or
remains LOW
OL
OE
.
RWD
IL
WCS
and V
go back
IH
t
t
and
WCS
RWD
RCD
RAD
IH
®
9
)