CY7C4215-25JC Cypress Semiconductor Corp, CY7C4215-25JC Datasheet - Page 3

• Manufacturer Part Number: CY7C4215-25JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4215-25JC

• Density: 8Kb
• Word Size: 18b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: LCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Lead Free Status / Rohs Status: Not Compliant

Selection Guide
Pin Definitions
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Operating Current (I
(mA) @ freq=20MHz
Density
Packages
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
Signal Name
0–17
0–17
(10x10/14x14)
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
68-pin PLCC
64-pin TQFP
CY7C4425
Description
64 x 18
CC2
)
Commercial
Industrial
(10x10/14x14)
68-pin PLCC
64-pin TQFP
CY7C4205
I/O
O
O
O
O
O
O
256 x 18
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus
Data outputs for an 18-bit bus
Enables the WCLK input
Enables the RCLK input
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
to V
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
V
When LD is LOW, D
ble-flag-offset register.
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
devices will have FL tied to V
to V
Not Cascaded - Tied to V
mode by strobing RT.
Cascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
CC
CC
SS
; it is synchronized to WCLK when V
7C42X5-10
; it is synchronized to RCLK when V
on all devices.
100
0.5
10
45
50
8
3
8
(10x10/14x14)
68-pin PLCC
64-pin TQFP
CY7C4215
512 x 18
3
0 - 17
SS
SS
7C42X5-15
(O
. Retransmit function is also available in standalone
.
0 - 17
66.7
CC
(10x10/14x14)
10
15
10
45
50
4
1
68-pin PLCC
64-pin TQFP
CY7C4225
. In standard mode of width expansion, FL is tied
1K x 18
) are written (read) into (from) the programma-
Function
CC
CC
/SMODE is tied to V
7C42X5-25
/SMODE is tied to V
CY7C4425/4205/4215
CY7C4225/4235/4245
(10x10/14x14)
68-pin PLCC
64-pin TQFP
CY7C4235
40
15
25
15
45
50
6
1
2K x 18
CC
/SMODE is tied to
CC
SS
/SMODE is tied
SS
(10x10/14x14)
7C42X5-35
68-pin PLCC
64-pin TQFP
SS
.
CY7C4245
; all other
.
4K x 18
28.6
20
35
20
45
50
7
2