CY7C4255-25AC Cypress Semiconductor Corp, CY7C4255-25AC Datasheet
CY7C4255-25AC
Specifications of CY7C4255-25AC
Available stocks
Related parts for CY7C4255-25AC
CY7C4255-25AC Summary of contents
Page 1
... FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4255/65 have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
Page 2
... Functional Description (continued) The CY7C4255/65 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Al- most Full, and Full. The Half Full flag shares the WXO pin. This flag is valid in the stand-alone and width-expansion configurations. In ...
Page 3
... HIGH, the FIFO’s outputs are in High Z (high-impedance) state. Dual-Mode Pin: Asynchronous Almost Empty/Almost Full flags – tied to V Synchronous Almost Empty/Almost Full flags – tied to V (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) 3 CY7C4255 CY7C4265 /SMODE is tied CC /SMODE is tied ...
Page 4
... IH V < V < Com’l 45 Ind 50 Com’l 10 Ind 15 Test Conditions T = 25° MHz 5. CY7C4255 CY7C4265 Ambient Temperature 0°C to +70°C 5V –40°C to +85°C 5V 7C42X5–25 7C42X5– 35 Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 0.4 2 ...
Page 5
... Min. Max. Min. Max. Min. Max. 100 4.5 4.5 3 0 [12 [12 [13] 12 /SMODE tied /SMODE tied [13] 12 /SMODE tied OHZ . PAF(E) 5 CY7C4255 CY7C4265 ALL INPUT PULSES 90% 90% 10% 10 4255–5 1.91V Min. Max. 66 ...
Page 6
... Skew Time between Read Clock and Write SKEW3 Clock for Programmable Almost Empty and Pro- grammable Almost Full Flags (Synchronous Mode only) 7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35 Min. Max. Min. Max. Min. Max. 8 /SMODE tied 4.5 6 CY7C4255 CY7C4265 Min. Max ...
Page 7
... NO OPERATION t REF [15] t SKEW2 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 7 CY7C4255 CY7C4265 ENH NO OPERATION t WFF t REF VALID DATA t OHZ 4255–6 4255–7 ...
Page 8
... The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW2 19. The first word is available the cycle after EF goes HIGH, always RSR t RSF t RSF t RSF [18] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW2 8 CY7C4255 CY7C4265 [17] OE=1 OE=0 4255– [19 4255–9 (maximum) = either 2 FRL CLK SKEW2 CLK ...
Page 9
... REN LOW OE t DATA IN OUTPUT REGISTER Q – REF REF SKEW1 DATA WRITE t WFF ENH A DATA READ 9 CY7C4255 CY7C4265 D1 t ENH ENS [18] t FRL t t REF SKEW2 D0 NO WRITE [14] DATA WRITE t WFF t ENH t ENS t A NEXT DATA READ 4255–10 4255–11 ...
Page 10
... REN Note: 20. PAE is offset = n. Number of data words into FIFO already = n. t CLKL t t ENS ENH t HF HALF FULL + 1 OR MORE ENS t CLKL t t ENS ENH t PAE WORDS IN FIFO t PAE t ENS 10 CY7C4255 CY7C4265 HALF FULLOR LESS 4255–12 n WORDS IN FIFO 4255–13 ...
Page 11
... If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW. 24. PAF offset = m. Number of data words written into FIFO already = 8192 25. PAF is offset = m. 26. 8192 m words in CY7C4255 and 16384 – m words in CY7C4265. 27. 8192 ( words in CY7C4255 and 16384 – CY7C4265. t CLKL t t ENS ...
Page 12
... Note PAF ENS ENH t ENS t CLKL t ENH t DH PAE OFFSET PAF OFFSET (m 1) words of the FIFO when PAF goes LOW. 12 CY7C4255 CY7C4265 FULL– M WORDS [26] IN FIFO t [30] PAF synch t SKEW3 t t ENS ENH 4255–16 PAE OFFSET – 4255–17 ...
Page 13
... ENS REN Write Expansion In Timing WXI WCLK Notes: 31. Write to Last Physical Location. 32. Read from Last Physical Location. t CLKL t ENH t A UNKNOWN PAE OFFSET Note Note Note XIS 13 CY7C4255 CY7C4265 PAF OFFSET PAE OFFSET 4255–18 4255–19 4255–20 4255–21 ...
Page 14
... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after XIS t PRT t RTR to update these flags. RTR 14 CY7C4255 CY7C4265 4255–22 4255–23 . RTR ...
Page 15
... Flag Operation The CY7C4255/65 devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchro- 0 – 17 nous. PAE and PAF are synchronous if V outputs after t . 0–17 OE Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN ...
Page 16
... Notes: 37 Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127). 38 Full Offset (Default Values: CY7C4255/CY7C4265 n = 127). nal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and t the retransmit pulse. With every valid read cycle after retransmit, pre- viously accessed data is read and the read pointer is incremented until it is equal to the write pointer ...
Page 17
... Width Expansion Configuration The CY7C4255/65 can be expanded in width to provide word widths greater than 18 in increments of 18. During width ex- pansion mode all control line inputs are common and all flags are available. Empty (Full) flags should be created by ANDing RESET (RS) DATA IN ( WRITE CLOCK (WCLK) ...
Page 18
... Depth Expansion Configuration (with Programmable Flags) The CY7C4255/65 can easily be adapted to applications re- quiring more than 8192/16384 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
Page 19
... AMBIENT TEMPERATURE( C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE ( C) 19 CY7C4255 CY7C4265 vs. AMBIENT A 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1.25 1. 5. 25° 3.0V IN 0.50 20.00 30 ...
Page 20
... CY7C4255–10AI CY7C4255–10JI 15 CY7C4255–15AC CY7C4255–15JC CY7C4255-15ASC CY7C4255–15AI CY7C4255–15JI 25 CY7C4255–25AC CY7C4255–25JC CY7C4255-25ASC CY7C4255–25AI CY7C4255–25JI 35 CY7C4255–35AC CY7C4255–35JC CY7C4255–35AI CY7C4255–35JI 16Kx18 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4265–10AC CY7C4265–10JC CY7C4365-10ASC CY7C4265– ...
Page 21
... Package Diagrams 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 21 CY7C4255 CY7C4265 51-85051-A ...
Page 22
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 68-Lead Plastic Leaded Chip Carrier J81 CY7C4255 CY7C4265 51-85046-B ...