JD54LS164BCA National Semiconductor, JD54LS164BCA Datasheet - Page 20
JD54LS164BCA
Manufacturer Part Number
JD54LS164BCA
Description
Manufacturer
National Semiconductor
Datasheet
1.JD54LS164BCA.pdf
(101 pages)
Specifications of JD54LS164BCA
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CLEAR
When the output control is low, the outputs are disabled to high impedance state.
however, sequential operation of the registers is not affected.
H
H
H
H
H
L
+
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
a, b, c,d = the level of steady state input at inputs A, B, C, or D, respectively.
Q
Q
H = high level (steady state), L = low level (steady state),
X = irrelevant (any input, including transitions)
Q
Q
↓
↓
Q
Shifting left requires external connection of Q
When the output control is low, the outputs are disabled to high impedance state.
however, sequential operation of the registers is not affected.
CONTROL
A0
An
A0
An
= transition from high to low level.
= transition from high to low level.
D
, Q
, Q
, Q
, Q
MODE
to C. Serial data is entered to input D.
LOAD/SHIFT
indicated steady state input conditions were established.
most recent
CONTROL
indicated steady state input conditions were established.
most recent
H
H
H
L
L
L
B0,
Bn
B0,
Bn
, Q
, Q
Q
Q
X
H
H
L
L
L
C0,
C0,
Cn
Cn
, Q
, Q
Q
Q
CLOCK
D0
D0
Dn
Dn
= the level of Q
= the level of Q
↓
↓
= the level of Q
= the level of Q
H
H
↓
↓
↓
↓
CLOCK
transition of the clock.
transition of the clock.
H
H
X
↓
↓
↓
INPUTS
FIGURE 2. Truth tables and timing diagrams - Continued.
SERIAL
INPUTS
H
X
X
X
X
L
SERIAL
A
A
A
A
H
X
X
X
X
, Q
L
, Q
, Q
, Q
Q
B
B
B
B
, Q
, Q
A
X
X
X
X
a
B
, Q
, Q
C
C
C
C
A
X
X
X
X
X
, or Q
a
, or Q
, or Q
, or Q
MIL-M-38510/306E
Q
PARALLEL
B
Device type 06
Device type 07
PARALLEL
B
X
X
X
X
b
C
to A, Q
B
X
X
X
X
X
D
b
D
D,
D,
, respectively, before the
, respectively, before the
respectively, before the
respectively, before the
20
Q
C
X
X
X
X
X
c
C
C
X
X
X
X
c
D
to B, and
D
X
X
X
X
X
d
D
X
X
X
X
d
d
Q
Q
Q
H
3 STATE OUTPUTS
L
a
L
A0
A0
A
Q
Q
Q
Q
H
a
L
A0
Bn
A0
Q
Q
Q
Q
A
Q
L
b
B0
B0
An
An
B
Q
Q
Q
Q
Q
OUTPUTS
Q
Q
Q
Q
Q
Q
b
L
c
B0
Cn
B0
An
An
C0
C0
B
Bn
Bn
C
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
L
d
Q
D0
D0
Cn
Cn
c
D
C0
Dn
C0
Bn
Bn
C
CASCADE
OUTPUT
Q
Q
Q
Q
Q
d
d
Q
Q
Q
Q
Q
D0
D0
Cn
Cn
D
L
d
D0
D0
Cn
Cn
D'
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