NHIXP430AC Intel, NHIXP430AC Datasheet - Page 23

• Manufacturer Part Number: NHIXP430AC
• Manufacturer: Intel

Specifications of NHIXP430AC

• Core Operating Frequency: 400MHz
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

6.0 Specification Changes
Note:
Figure 2.
Figure 3.
Affected
December 2008
Order Number: 316847; Revision:
Docs:Intel
3) Software must wait for at least 2 cycles. Then configure the DCALADDR register
(Hex offset: CC00 F504) with bit[1:0]=’01’, and bit[9:7]=’111’. (To issue a OCD Exit
command)
Other fields in the DCALCSR and DCALADDR registers should be left as ‘zero’ (default
value after reset). The ‘Qoff’, ‘RDQS’, and ‘DQS’ fields are mapped to DCALADDR
register bit[12:10] respectively.
The DLL enabled is configured through writing ‘0100’ to the SDIR register. The Rtt is
configured by writing to SDCR0 register bit[5:4].
Procedure to modify the bootloader (for EMRS OCD instruction):
Solution for Redboot* platform (packages/hal/arm/xscale/ixdp435/current/include/
hal_ixp425.h) as illustrated in
Define DDR_DCALCSR and DDR_DCALADDR Registers
Solution for Redboot* platform (packages/hal/arm/xscale/ixdp435/current/include/
hal_platform_setup.h). Add in the EMRS code (bold) in between Step 14 and Step 15,
as illustrated in
EMRS Code Example
// Step 14. Issue mode register set w/o DLL reset
//*********Added steps:EMRS OCD Calibration Default********
//*********Added steps:EMRS OCD Calibration Mode Exit******
// Step 15. Start normal operation
®
IXP43X Product Line of Network Processors Developer’s Manual.
mov
str
DELAY 0x100000, r1
ldr
ldr
str
ldr
str
DELAY 0x100000, r1
ldr
str
DELAY 0x100000, r1
str
005US
Figure
r1, #DDR_SDIR_MODE_SET_NO_RESET
r1, [r0, #IXP_DDR_SDIR]
r2, [r0, #IXP_DDR_DCALADDR] //save DCALADDR value in r2 before modifying
r1, = 0x01000003
r1, [r0, #IXP_DDR_DCALCSR]
r1, =0x00000381
r1, [r0, #IXP_DDR_DCALADDR]
r1, =0x00000001
r1, [r0, #IXP_DDR_DCALADDR]
r2, [r0, #IXP_DDR_DCALADDR] //restore original DCALADDR value
3.
Figure
//set bit24=1 for SDRAM Enable
//set bits[0:1] for EMRS OCD Default
//set bits [9:7] and bit 0 for EMRS OCD Default
//set bit 0 only for exit
2.
Intel
®
IXP43X Product Line of Network Processors
Specification Update
23