CY7C53150-20AIT Cypress Semiconductor Corp, CY7C53150-20AIT Datasheet

CY7C53150-20AIT

Manufacturer Part Number
CY7C53150-20AIT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C53150-20AIT

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-10001 Rev. *F
Features
Notes
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior. See the
2. Maximum Junction Temperature is 105°C. T
Three 8-bit pipelined processors for concurrent processing
of application code and network traffic
11-pin I/O port programmable in 34 modes for fast application
program development
Two 16-bit timer/counters for measuring and generating I/O
device waveforms
5-pin communication port that supports direct connect and
network transceiver interfaces
Programmable pull ups on IO4–IO7 and 20 mA sink current
on IO0–IO3
Unique 48-bit ID number in every device to facilitate network
installation and management
Low operating current; sleep mode operation for reduced
current consumption
0.35 μm Flash process technology
5.0V operation
Logic Block Diagram
Manual
for more details.
Control Processor
Media Access
(CY7C53120)
Application
[1]
Processor
Processor
2 KB RAM
Network
Flash
ROM
Junction
= T
198 Champion Court
Ambient
+ V•I•
θ
Address Bus
JA
. 32-pin SOIC
Data Bus
Internal
Internal
(0:15)
(0:7)
Neuron Chip Network Processor
On-chip LVD circuit to prevent nonvolatile memory corruption
during voltage drops
2,048 bytes of SRAM for buffering network data, system, and
application data storage
512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096
bytes (CY7C53120E4) of Flash memory with on-chip charge
pump for flexible storage of configuration data and appli-
cation code
Addresses up to 58 KB of external memory (CY7C53150)
10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
Maximum input clock operation of 20 MHz (CY7C53150),
10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a
–40°C to 85°C
64-pin TQFP package (CY7C53150)
32-pin SOIC or 44-pin TQFP package (CY7C53120)
θ
JA
= 51C/W. 44-pin TQFP
San Jose
[2]
temperature range
Communications
,
CY7C53150, CY7C53120
CA 95134-1709
Clock, and
Counters
Oscillator,
I/O Block
2 Timer/
Control
θ
Port
JA
= 43C/W. 64-pin TQFP
Revised November 20, 2009
External
Address/Data Bus
(CY7C53150)
Neuron Technical Reference
CP4
CP0
IO10
IO0
CLK1
CLK2
SERVICE
RESET
θ
JA
408-943-2600
= 44C/W.
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Related parts for CY7C53150-20AIT

CY7C53150-20AIT Summary of contents

Page 1

... Flash memory with on-chip charge pump for flexible storage of configuration data and appli- cation code ■ Addresses external memory (CY7C53150) ■ (CY7C53120E2 (CY7C53120E4) of ROM containing LonTalk network protocol firmware ■ Maximum input clock operation of 20 MHz (CY7C53150), 10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a – ...

Page 2

... Programmable Glitch Filter Values .................................7 Receiver ......................................................................... 7 Differential Receiver .......................................................7 Electrical Characteristics.....................................................8 Document #: 38-10001 Rev. *F CY7C53150, CY7C53120 LVI Trip Point .......................................................................8 External Memory Interface Timing — CY7C53150, VDD ± 10% .......................................................................................9 Differential Transceiver Electrical Characteristics.................................................... 9 Ordering Information......................................................... 11 Package Diagrams............................................................. 12 Document History Page .................................................... 15 Sales, Solutions, and Legal Information ......................... 15 Worldwide Sales and Design Support ...

Page 3

... KB with the address space mapped internally. LonWorks nodes that require large application programs can take advantage of this external memory capability. The CY7C53150 Neuron chip is an exact replacement for the Motorola MC143150Bx and Toshiba TMPN3150B1 devices. The CY7C53120E2 Neuron chip is an exact replacement for the Motorola MC143120E2 device since it contains the same firmware in ROM ...

Page 4

... IO8 IO0 7 26 IO9 SERVICE IO10 CP4 CP3 CP1 SS CLK2 14 19 CP0 CLK1 CP2 SS Document #: 38-10001 Rev. *F Figure 2. 32-Pin SOIC and 44-Pin QFP IO6 35 IO5 [ RESET IO4 DD IO3 43 [ PIN 1 INDICATOR CY7C53150, CY7C53120 [ CP1 21 CP0 CP2 18 CY7C53120Ex-yyAI [ CLK1 15 CLK2 [ Page 4 [+] Feedback ...

Page 5

... DD 40, 41, 44 pins must 8,19, 21, 25 13, 16, 23 28, 29, 30, 31, 32 19, 20, 17, 21, 22 20, 21, 18, 24 18, 27, 48, 49 CY7C53150, CY7C53120 CY7C53120xx CY7C53120xx SOIC-32 Pin No. TQFP-44 Pin No 30, 29, 28 42, 36, 35, 32 ...

Page 6

... All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120 family, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150, the system firmware must be present in the first off-chip nonvolatile memory such as Flash, EPROM, EEPROM, or NVRAM. These devices must be programmed in a device programmer before board assembly ...

Page 7

... Differential Receiver (End-to-End) Absolute [9, 10] 700 ns Symmetry 1350 ns Filter (F) 2600 ns 0 Figure 3. : Time from input switching states from high to low to output switching states. PHL CY7C53150, CY7C53120 Max (t – PLH PHL 35 150 250 400 ⎮ ≥ CP0 – CP1 + 200 mV hys ≤ ...

Page 8

... CY7C53120E2, CY7C53120E4, and CY7C53150 Notes 11. Standard outputs are IO4–IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < load.) For CY7C53150, standard outputs also include A0–A15, D0–D7, E, and R/W. 12. IO4–IO7 and SERVICE have configurable pull ups. RESET has a permanent pull up. ...

Page 9

... External Memory Interface Timing — CY7C53150, V Parameter Description t Memory Cycle Time (System Clock Period) cyc [16] PW Pulse Width, E High EH [16] PW Pulse Width, E Low EL t Delay, E High to Address Valid AD t Address Hold Time After E High AH t Delay, E High to R/W Valid Read RD t R/W Hold Time Read After E High ...

Page 10

... OH V – Measured low output drive level 1 LOAD Address Address DSR Data In t DHR t t DDW DHR t DHZ Memory READ Memory WRITE CY7C53150, CY7C53120 t AD Address DDW t t DDZ DDZ t DHZ t DHW t DHW Data Out Data Out Memory WRITE Page 10 [+] Feedback ...

Page 11

... Notes 23. All parts contain SRAM. 24. CY7C53120E2 firmware is bit-for-bit identical with Motorola MC143120E2 firmware. 25. CY7C53150 may be used with 20-MHz input clock only if the firmware in external memory is version 13 or later. 26. CY7C53120E4 requires upgraded LonBuilder® and NodeBuilder® software. Document #: 38-10001 Rev trip - ...

Page 12

... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 1.40±0.05 A SEE DETAIL CY7C53150, CY7C53120 0° MIN. R. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE R. 0.08 MIN. ...

Page 13

... TYP. STAND-OFF 33 0.05 MIN. 0.15 MAX 0.08 MIN. 12°±1° 0.20 MAX. (8X) 1.40±0.05 A SEE DETAIL CY7C53150, CY7C53120 0° MIN. R 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE 0°-7° 0.20 MIN. 0.60±0.15 1.00 REF. A DETAIL 51-85046-*C Page 13 ...

Page 14

... Figure 13. 32-Pin (450-Mil) SOIC S32.45 1 DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.004[0.102] MIN. SEATING PLANE - - CY7C53150, CY7C53120 MIN. MAX. PART # S32.45 STANDARD PKG. SZ32.45 LEAD FREE PKG. 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*C Page 14 [+] Feedback ...

Page 15

... Document History Page Document Title: CY7C53150, CY7C53120 Neuron Chip Network Processor Document Number: 38-10001 Submission REV. ECN NO. Date ** 111472 11/28/01 *A 111990 02/06/02 *B 114465 04/24/02 *C 115269 04/26/02 *D 124450 03/25/03 *E 837840 3/14/07 *F 2811866 11/20/2009 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...

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