GWIXP465AB Intel, GWIXP465AB Datasheet - Page 19
GWIXP465AB
Manufacturer Part Number
GWIXP465AB
Description
Manufacturer
Intel
Datasheet
1.GWIXP465AB.pdf
(163 pages)
Specifications of GWIXP465AB
Core Operating Frequency
266MHz
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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3.1
3.1.1
Intel
Document Number:
®
Table 3.
IXP45X and Intel
Key Functional Units
The following sections briefly describe the functional units and their interaction in the system. For
more detailed information, refer to the Intel
Processors Developer’s Manual.
Unless otherwise specified, the functional descriptions apply to all of the IXP45X/IXP46X
network processors. For specific information on supported interfaces, refer to
For model-specific block diagrams, see
page
Network Processor Engines (NPEs)
The network processor engines (NPEs) are dedicated-function processors containing hardware
coprocessors integrated into the IXP45X/IXP46X network processors. The NPEs are used to off
load processing function required by the Intel XScale core.
These NPEs are high-performance, hardware-multi-threaded processors with additional local-
hardware-assist functionality used to off load highly processor-intensive functions such as MII
(MAC), CRC checking/generation, AAL 2 segmentation and re-assembly, AES, AES-CCM, DES,
DES3, SHA-1/256/384/512, MD5, etc.
All instruction code for the NPEs are stored locally and is accessed using a dedicated instruction
memory bus. Likewise, a separate dedicated data memory bus allows accesses to local code store
as well as DDR SDRAM via the AHB bus.
These NPEs support processing of the dedicated peripherals that can include:
Table 3
IXP46X network processors. These configurations are determined by the factory programmed fuse
settings or by software that configures the part during boot-up.
Network Processor Functions (Sheet 1 of 2)
Configuration 0
(default)
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
•
•
•
306261-002
®
One UTOPIA Level 2 (Universal Test and Operation PHY Interface for ATM) interface
Two High-Speed Serial (HSS) interfaces
Up to three Media-Independent Interface (MII), up to six Serial Media Independent Interfaces
(SMII)/Source-Synchronous Serial Media Independent Interfaces (SS-SMII), or some
combination of each.
18.
IXP46X Product Line of Network Processors Datasheet
Device
specifies the possible combination of interfaces for the NPEs contained on the IXP45X/
UTOPIA
X
X
X
X
X
HSS
X
X
X
X
X
X
X
MII /SMII
MII
MII
Figure 1 on page
A
®
IXP45X and Intel
MII / 4 SMII
4 SMII
4 SMII
SMII
SMII
SMII
MII
MII
B
16,
MII / SMII
SMII
SMII
MII
MII
MII
MII
MII
Figure 2 on page
C
®
IXP46X Product Line of Network
AES / DES
/ DES3
X
X
X
X
X
X
X
Functional Overview
Table 1 on page
17, and
HDLC SHA MD-5
8
8
8
8
8
8
8
Figure 3 on
May 2005
X
X
X
X
X
X
X
14.
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