SSDPAPS0002G1 Intel, SSDPAPS0002G1 Datasheet - Page 19

• Manufacturer Part Number: SSDPAPS0002G1
• Manufacturer: Intel
• Type: Solid State Driver

Specifications of SSDPAPS0002G1

• Density: 2GByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 168
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Compliant

Intel® Z-P140 PATA SSD
Table 16.
October 2008
Order Number: 318890-003US
DIOR#
DIOW#
DMACK#
DMARQ
HRESET#
IOCS16#
INTRQ
IORDY
PDIAG#
PSYNC_CSEL#
PWE#
RESET#
Symbol
PATA Signal Descriptions (Continued)
Input / Output
Input / Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
I/O Data Read Enable is the strobe signal asserted by the host to read device
registers or the data port.
I/O Data Write Enable is the strobe signal asserted by the host to write device
registers or the data port.
DIOW shall be negated by the host prior to the initiation of an Ultra DMA
burst. STOP shall be negated by the host before the data is transferred in an
Ultra DMA burst. The assertion of STOP by the host during an Ultra DMA burst
signals the termination of the Ultra DMA burst.
DMA Acknowledge, used by the host in response to DMARQ to either
acknowledge that data has been accepted, or that the data is available.
DMA request. This signal, used for DMA data transfers between host and
device, shall be asserted by the device when it is ready to transfer data to or
from the host. For multi word DMA transfers, the direction of data transfer is
controller by DIOR# and DIOW#. This signal is used in a “handshake” manner
with DMACK#. For example, the device shall wait until the host asserts
DMACK# before negating DMARQ and re-asserting DMARQ if there is more
data to transfer.
When a DMS operation is enabled, CS0# and CS1# shall not be asserted and
transfers shall be 16 bits wide. This signal shall be release when the device is
not selected.
Host reset.
16-bit I/O transfer.
Drive interrupt request.
I/O channel ready.
Passed diagnostics.
Cable Select for master/slave, spindle synch, or True-IDE chip.
Memory Write Enable or Service Mode Select.
Refers to the hardware reset that is used by the host to reset the device.
Description
Intel® Z-P140 PATA SSD
Product Manual
19