LQ104V1DG21 Sharp Electronics, LQ104V1DG21 Datasheet - Page 11

• Manufacturer Part Number: LQ104V1DG21
• Manufacturer: Sharp Electronics

Specifications of LQ104V1DG21

• Lead Free Status / Rohs Status: Compliant

7. Timing Characteristics of input signals
Note) In case of lower frequency, the deterioration of display quality, flicker etc.,may be occurred.
7-2. Horizontal display position
Timing diagrams of input signal are shown in Fig.2 - ①∼③ .
7-1. Timing characteristics
to the rising edge of ENAB signal is displayed at the left end of the active area.
Note) When ENAB is fixed "Low", the display starts from the data of C104(clock) as shown
Enable signal Setup time
Hsync-Enable signal
phase difference
Clock
Data
Horizontal
sync. signal
Vertical
sync. signal
Horizontal display period
Hsync-Clock
phase difference
Hsync-Vsync
phase difference
The horizontal display position is determined by ENAB signal and the input data corresponding
When the phase difference is below 104 clock, keep the “High level of ENAB is signal longer
Than 104-The. If it will not be keeped, the display starts from the data of C104(clock).
in Fig.2-①∼③. Be careful that the module does not work when ENAB is fixed "High".
Parameter
Parameter
Pulsewidth
Pulse width
Frequency
High time
Low time
Setup time
Hold time
Cycle
Pulse width
Cycle
Symbol Mode
symbol
1/Tc
THp
THe
TVp
THd
TVh
THc
Tep
Tch
Tdh
Tes
Tds
TH
Tcl
TV
Min.
480
400
350
all
〃
〃
〃
〃
〃
〃
〃
all
〃
〃
〃
44
5
2
30.00
Min.
750
515
446
447
640
10
10
10
Typ.
−
5
5
2
1
0
640
−
−
25.18
31.78
TH-664 clock
Typ.
800
525
449
449
640
Tc-10
Max.
−
−
−
−
96
−
−
−
640
TH-THp clock
Tc-10
28.33
Max.
clock
900
200
560
480
510
640
Unit
−
−
−
−
−
34
ns
Remark
clock
clock
clock
MHz
Unit
line
line
line
line
μs
ns
ns
ns
ns
ns
Remark