LQ025Q3DW02 Sharp Electronics, LQ025Q3DW02 Datasheet - Page 13

• Manufacturer Part Number: LQ025Q3DW02
• Manufacturer: Sharp Electronics

Specifications of LQ025Q3DW02

• Lead Free Status / Rohs Status: Compliant

Note 3)
R/W
W
VSYNC
HSYNC
Vertical Porch(R17h)(POR=0002h)
VBP8-0 : Set the delay period from falling edge of VSYNC to first valid line.
POR
HSYNC
Pixel
Data
DOTCLK
DC
1
VBP8
0
0
0
1
1
1
1
IB15
0
0
VBP7
T
0
0
0
0
0
0
1
VBP
IB14
0
0
: Set by VBP8-0
T
VBP6
HBP
＊
0
0
0
0
0
1
IB13
: Set by HBP5-0
0
0
VBP5
＊
＊
0
0
0
1
1
IB12
0
0
VBP4
IB11
：
：
：
＊
＊
0
0
0
1
1
0
0
VBP3
IB10
＊
＊
0
0
0
1
1
0
0
VDISP=240
Vcycle
VBP2
IB9
＊
＊
0
0
0
0
0
1
1
Hcycle
VBP8
VBP1
HDISP=320
IB8
0
＊
＊
0
0
1
1
1
320
VBP7
VBP0
IB7
0
＊
＊
0
1
0
0
1
VBP6
IB6
No. of clock cycle of HSYNC
0
(only allow when CAD=0)
VBP5
IB5
0
Reserved
Reserved
Step = 1
t
319
320
VFP
：
：
0
1
2
VBP4
IB4
t
0
HFP
VBP3
IB3
0
LD-19X15B -10
VBP2
IB2
0
VBP1
IB1
1
VBP0
IB0
0