ICS83026AMI IDT, Integrated Device Technology Inc, ICS83026AMI Datasheet
ICS83026AMI
Specifications of ICS83026AMI
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ICS83026AMI Summary of contents
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... SOIC footprint makes this device ideal for use in applications with limited board space. Block Diagram Q0 Pulldown CLK Pullup nCLK Q1 ICS83026AMI REVISION C AUGUST 26, 2009 Features • Two LVCMOS/LVTTL outputs • Differential CLK/nCLK input pair • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • ...
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... R Input Pulldown Resistor PULLDOWN Power Dissipation Capacitance C PD (per output) R Output Impedance OUT ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Type Description No connect. Pulldown Non-inverting differential clock input. Pullup Inverting differential clock input. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. ...
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... Common Mode Input Voltage; V CMR NOTE 1, 2 NOTE 1: V should not be less than -0.3V. IL NOTE 2: Common mode voltage is defined as V ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Rating 4.6V -0. -0. 112.7°C/W (0 lfpm) -65°C to 150°C = 3.3V ± 0.3V -40° ...
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... NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER = 3.3V ± 0.3V -40° ...
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... As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
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... Core/3.3V LVCMOS Output Load AC Test Circuit tsk(o) Output Skew Q0 PERIOD t PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period ICS83026AMI REVISION C AUGUST 26, 2009 SCOPE Qx Differential Input Level Part-to-Part Skew 100% Output Rise/Fall Time 6 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER V DD nCLK V Cross Points PP CLK GND Par ...
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... R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/ 0.609. ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER / Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input ...
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... R3 and R4 can be 0 Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Please consult with the vendor of the driver component to confirm the and V driver termination requirements. For example, in Figure 2A, the input ...
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... Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83026I is: 416 Pin-to-pin compatible with the MC100EPT26 Package Outline and Package Dimensions Package Outline - M Suffix for 8 Lead SOIC ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER θ by Velocity JA 0 200 112.7° ...
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... Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER Package ...
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... Differential DC Characteristics Table - updated NOTES Characteristics Tables - added Additive Phase Jitter row. 5 Added Additive Phase Jitter Plot. 8 Updated Differential Clock Input Interface. Converted datasheet format. ICS83026AMI REVISION C AUGUST 26, 2009 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER IN Ω max row. OUT 11 Ω 4pF max. to 4pF typical. Added 5 min. and © ...
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ICS83026I Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...