MT47H16M16BG-3 Micron Technology Inc, MT47H16M16BG-3 Datasheet - Page 121

• Manufacturer Part Number: MT47H16M16BG-3
• Manufacturer: Micron Technology Inc

Specifications of MT47H16M16BG-3

• Lead Free Status / Rohs Status: Compliant

Figure 78: RESET Function
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
Bank address
Command
Address
ODT
DQS 3
DM 3
CK#
CKE
A10
DQ 3
R
CK
TT
Bank a
READ
Col n
T0
High-Z
High-Z
Notes:
NOP 2
T1
1. V
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
5. Initialization timing is shown in Figure 41 (page 82).
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-
ate configuration (x4, x8, x16).
completion of the burst.
DD
Bank b
Col n
READ
, V
T2
DDL
, V
DDQ
NOP 2
Indicates a break in
time scale
T3
, V
DO
TT
, and V
DO
NOP 2
T4
121
System
DO
RESET
REF
must be valid at all times.
t DELAY
Unknown
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR2 SDRAM
1
R
TT
On
High-Z
High-Z
Transitioning Data
t CL
t CK
©2003 Micron Technology, Inc. All rights reserved.
Start of normal 5
initialization
t CL
sequence
NOP 2
Ta0
4
T = 400ns (MIN)
t CKE (MIN)
All banks
Tb0
PRE
Don’t Care
High-Z
t RPA
Reset