ADV7330KST Analog Devices Inc, ADV7330KST Datasheet - Page 23

• Manufacturer Part Number: ADV7330KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7330KST

• Operating Supply Voltage (typ): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

REV. B
SR7–
SR0
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
Register
SD Timing Register 0
SD Timing Register 1
SD F
SD F
SD F
SD F
SD F
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
Bit Description
SD Slave/Master Mode
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Min. Luma Value
SD Timing Reset
SD HSYNC Width
SD HSYNC to VSYNC Delay
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only)
VSYNC Width (Mode 2 Only)
HSYNC to Pixel Data Adjust
Extended Data on Even Fields
Extended Data on Even Fields
Data on Odd Fields
Data on Odd Fields
Pedestal on Odd Fields
Pedestal on Odd Fields
Pedestal on Even Fields
Pedestal on Even Fields
HSYNC
VSYNC
t
LINE 1
B
Figure 15. Timing Register 1 in PAL Mode
t
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
17
25
17
25
x
0
0
1
1
x
x
x
x
x
x
x
x
x
16
24
16
24
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
15
23
15
23
0
0
1
1
0
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
–23–
14
22
14
22
0
1
0
1
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
13
21
13
21
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
12
20
12
20
0
0
1
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
t
C
11
19
11
19
0
1
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
LINE 313
10
18
10
18
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
Register Setting
Slave Mode
Master Mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No Delay
2 Clk Cycles
4 Clk Cycles
6 Clk Cycles
– 40 IRE
– 7.5 IRE
A low-high-low transition will reset the
internal SD timing counters.
T
T
T
T
T
T
T
T
T
T
1 Clk Cycle
4 Clk Cycles
16 Clk Cycles
128 Clk Cycles
0 Clk Cycles
1 Clk Cycle
2 Clk Cycles
3 Clk Cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
Extended Data Bit 15–8
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1
will disable pedestal on the
line number indicated by the
bit settings.
A
A
A
A
B
B
B
B
C
C
= 1 Clk Cycle
= 4 Clk Cycles
= 16 Clk Cycles
= 128 Clk Cycles
= 0 Clk Cycle
= 4 Clk Cycles
= 8 Clk Cycles
= 18 Clk Cycles
= T
= T
LINE 314
B
B
+ 32 µs
ADV7330
Reset Values
08h
00h
16h
7Ch
F0h
21h
00h
00h
00h
00h
00h
00h
00h
00h
00h