DS92LV8028TUF National Semiconductor, DS92LV8028TUF Datasheet - Page 3
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DS92LV8028TUF
Manufacturer Part Number
DS92LV8028TUF
Description
Manufacturer
National Semiconductor
Datasheet
1.DS92LV8028TUF.pdf
(16 pages)
Specifications of DS92LV8028TUF
Number Of Elements
8
Number Of Receivers
10
Number Of Drivers
1
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Output Type
Serializer
Differential Output Voltage
550mV
Transmission Data Rate
660Mbps
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS92LV8028TUF
Manufacturer:
NS
Quantity:
745
Company:
Part Number:
DS92LV8028TUF/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
SER/DES SUPPLY CURRENT (apply to pins DVDD, PVDD and AVDD)Over recommended operating supply and temperature
ranges unless otherwise specified.
Symbol
Symbol
Symbol
t
Electrical Characteristics
t
(Ind. Ch)
t
Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2) (Note 3)
(Master)
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3)
t
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3)
CLKT
t
t
TCIH
TCIL
t
I
I
TCP
t
t
t
t
t
t
LLHT
LHLT
t
t
I
JIT
CCXD
CCXD
HZD
LZD
ZHD
ZLD
SPD
PLD
DIH
DIS
CCD
TCLK Input Transition
Transmit Clock High
Transmit Clock Low
SYNC Pattern Delay,
DO
DO
DIN (0-9) Hold from
Serializer PLL Lock
TCLK Input Jitter
DIN (0-9) Setup to
TRI-STATE Delay
TRI-STATE Delay
Supply Current Powered Down
Transmit Clock
Worst Cast Power Saving Per
Transition Time
Transition Time
DO
Time, Figure 6
Worst Case Supply Current
DO
Parameter
Low-to-High
High-to-Low
±
HIGH Delay
±
LOW Delay
Parameter
(Checker-board pattern)
Bus LVDS
Bus LVDS
Period
Figure 8
TRI-STATE to
TRI-STATE to
Time
Time
Time
±
TCLK
TCLK
±
Channel Disabled
(SYNC pattern)
HIGH to
Supply Current
LOW to
Parameter
C
C
C
C
L
L
L
L
Conditions
=10pF to GND
=10pF to GND
=10pF to GND
=10pF to GND
Conditions
R
R
R
R
Figure 3
Figure 2
Figure 4
Figure 5
(Note 5)
L
L
L
L
= 100Ω,
= 100Ω,
= 100Ω
= 100Ω
(Continued)
MS_PWDN = 0.1V,
MS_PWDN = 3V,
PWDNn = 0V
V
V
Conditions
R
R
DEN = 0V
CC
CC
L
L
Figure 1
DOn+, DOn-, DEN
= 100 Ω
= 100 Ω
DINn(0-9), TCLK
= 3.6V,
= 3.6V,
TCLK, SYNCn,
DOn+, DOn-,
DOn+, DOn-
MS_PWDN
Pin/Freq.
Pin/Freq.
TCLK
3
f = 25 MHz
f = 66 MHz
f = 25MHz
f = 66MHz
Pin/Freq.
66 MHz
25 MHz
510*t
15.15
4*t
Min
Min
198
115
40
40
1.5
1.5
TCP
TCP
Typ
Typ
236
232
50
50
5.7
6.9
6.2
5.8
3
Min
Typ
145
175
148
263
3.6
513*t
22
6
5*t
Max
Max
400
400
40
60
60
80
12
12
12
12
6
TCP
TCP
www.national.com
Max
166
350
200
Units
Units
ps
Units
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
mA
mA
mA
mA
%
%
µA
rms