MT46V16M16TG-5BLIT Micron Technology Inc, MT46V16M16TG-5BLIT Datasheet - Page 80
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MT46V16M16TG-5BLIT
Manufacturer Part Number
MT46V16M16TG-5BLIT
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M16TG-5BLIT.pdf
(93 pages)
Specifications of MT46V16M16TG-5BLIT
Lead Free Status / Rohs Status
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Figure 43:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-READ – Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ com-
t
mand will not mask these two data elements.
DI
WTR is referenced from the first positive CK edge after the last data-in pair.
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
T2n
78
Bank a,
READ
Col n
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CL = 2
CL = 2
CL = 2
T4
NOP
256Mb: x4, x8, x16 DDR SDRAM
Transitioning Data
T5
NOP
DO
DO
DO
©2003 Micron Technology, Inc. All rights reserved.
n
n
n
T5n
T6
NOP
Operations
Don’t Care
T6n
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