LM63EVAL National Semiconductor, LM63EVAL Datasheet - Page 6

• Manufacturer Part Number: LM63EVAL
• Manufacturer: National Semiconductor

Specifications of LM63EVAL

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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f
t
t
t
t
t
t
t
t
t
t
t
t
SMB
LOW
HIGH
R
F
OF
TIMEOUT
SU:DAT
HD:DAT
HD:STA
SU:STO
SU:STA
BUF
Symbol
SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
80 pF. Boldface limits apply for T
switching characteristics of the LM63 fully meet or exceed the published specifications of the SMBus version 2.0. The following
parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM63. They adhere to but are
not necessarily the same as the SMBus bus specifications.
SMBus Clock Frequency
SMBus Clock Low Time
SMBus Clock High Time
SMBus Rise Time
SMBus Fall Time
Output Fall Time
SMBData and SMBCLK Time Low for Reset
of Serial Interface See (Note 13)
Data In Setup Time to SMBCLK High
Data Out Hold Time after SMBCLK Low
Hold Time after (Repeated) Start Condition.
After this period the first clock is generated.
Stop Condition SMBCLK High to SMBDAT
Low (Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
SMBus Free Time between Stop and Start
Conditions
Parameter
SMBus Timing Diagram for SMBCLK and SMBDAT Signals
A
= T
J
; T
MIN
≤ T
A
≤ T
DD
MAX
= +3.0 VDC to +3.6 VDC, C
From V
From V
(Note 11)
(Note 12)
C
L
; all other limits T
6
= 400 pF, I
IN(0) max
IN(1) min
O
to V
Conditions
to V
= 3 mA
A
IN(1) min
IN(0) max
= T
J
= +25˚C, unless otherwise noted. The
L
(load capacitance) on output lines =
(Note 8)
Limits
100
250
250
300
930
100
4.7
4.0
0.3
4.0
4.7
4.7
10
50
25
35
1
20057004
kHz (max)
kHz (min)
ms (max)
µs (max)
µs (max)
µs (max)
ns (max)
ms (min)
ns (max)
µs (min)
µs (min)
ns (min)
ns (min)
µs (min)
ns (min)
µs (min)
µs (min)
(Limit)
Units