DS4426T+T&R Maxim Integrated Products, DS4426T+T&R Datasheet - Page 12

• Manufacturer Part Number: DS4426T+T&R
• Description: IC DAC I2C-MARGINING 4CH 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS4426T+T&R

• Data Interface: I²C
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Number Of Bits: -
• Settling Time: -

Quad-Channel, I
Three Channels of Power-Supply Tracking
Figure 6. I
Figure 7. I
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
12
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
A)
B)
TYPICAL I
EXAMPLE I
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
START
SINGLE-BYTE WRITE
-WRITE REGISTER F9h TO 00h
SINGLE-BYTE READ
-READ REGISTER F8h
______________________________________________________________________________________
STOP
2
C WRITE TRANSACTION
2
MSB
C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED)
2
2
1
C Timing Diagram
C Communication Examples
t
BUF
0
START
0
ADDRESS*
SLAVE
t
HD:STA
1
IL(MAX)
0
t
START
LOW
START
I
AND V
2
A1
C Communication
IH(MIN)
1 0 0 1 0 0 0 0
1 0 0 1 0 0 0 0
A0
t
R
READ/
WRITE
90h
90h
.
LSB
R/W
t
HD:DAT
SLAVE
ACK
2
SLAVE
SLAVE
ACK
ACK
C-Margining IDACs with
MSB
b7
1 1 1 1 1 0 0 1
1 1 1 1 1 0 0 0
t
HIGH
b6
F9h
F8h
REGISTER/MEMORY ADDRESS
t
F
b5
t
SU:DAT
b4
SLAVE
SLAVE
ACK
ACK
b3
0 0 0 0 0 0 0 0
REPEATED
b2
START
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
REPEATED
b1
START
LSB
b0
1 0 0 1 0 0 0 1
SLAVE
t
SU:STA
ACK
91h
SLAVE
ACK
t
HD:STA
STOP
MSB
b7
SLAVE
ACK
b6
b5
DATA
b4
DATA
b3
MASTER
t
NACK
SP
b2
b1
STOP
LSB
b0
t
SU:STO
SLAVE
ACK
STOP