EVAL-AD5445EB Analog Devices Inc, EVAL-AD5445EB Datasheet - Page 28

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EVAL-AD5445EB

Manufacturer Part Number
EVAL-AD5445EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-AD5445EB

Lead Free Status / Rohs Status
Not Compliant
AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
0.15
0.05
4.50
4.40
4.30
PIN 1
Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP]
BSC
0.65
16
1
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AB
5.10
5.00
4.90
0.10
Dimensions shown in millimeters
0.30
0.19
9
8
1.20
MAX
SEATING
PLANE
BSC
6.40
(RU-16)
0.20
0.09
INDICATOR
SEATING
PLANE
1.00
0.85
0.80
PIN 1
12° MAX
Figure 65. 20-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
BSC
0.50
BSC SQ
4.00
VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
TOP
0.80 MAX
0.65 TYP
0.20
REF
Dimensions shown in millimeters
4 × 4 mm Body, Very Thin Quad
BCS SQ
0.75
0.60
0.45
Rev. A | Page 28 of 32
3.75
0.05 MAX
0.02 NOM
(CP-20-1)
COPLANARITY
MAX
COPLANARITY
0.75
0.55
0.35
0.60
0.08
0.15
0.05
MAX
0.60
PIN 1
Figure 64. 20-Lead Thin Shrink Small Outline Package [TSSOP]
15
11
0.10
16
10
20
1
BSC
0.30
0.23
0.18
0.65
INDICATOR
0.30
0.19
20
6
COMPLIANT TO JEDEC STANDARDS MO-153AC
PIN 1
6.60
6.50
6.40
Dimensions shown in millimeters
5
1
1.20 MAX
0.25 MIN
2.25
2.10 SQ
1.95
11
10
SEATING
PLANE
(RU-20)
4.50
4.40
4.30
0.20
0.09
6.40 BSC
0.75
0.60
0.45