EVAL-AD7482CB Analog Devices Inc, EVAL-AD7482CB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD7482CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7482CB

• Lead Free Status / Rohs Status: Not Compliant

AD7482
Data must not be read from the AD7482 while a conversion is
taking place. For this reason, if operating the AD7482 at through-
put speeds greater than 2.5 MSPS, it is necessary to tie both the
CS pin and RD pins on the AD7482 low and use a buffer on the
data lines. This situation may also arise in the case where a read
operation cannot be completed in the time after the end of one
conversion and the start of the quiet period before the next
conversion.
The maximum slew rate at the input of the ADC must be limited to
500 V/μs while BUSY is low to avoid corrupting the ongoing
conversion. In any multiplexed application where the channel is
switched during conversion, this is to happen as soon as possible
after the BUSY falling edge.
Reading Data from the AD7482
Data is read from the part via a 13-bit parallel data bus with the
standard CS signal and RD signal. The CS signal and RD signal are
internally gated to enable the conversion result onto the data bus.
The data lines D0 to D12 leave their high impedance state when
both the CS and RD are logic low. Therefore, CS may be perma-
nently tied logic low if required, and the RD signal may be used
to access the conversion result.
tion called t
after any data bus activity before the next conversion is initiated.
Writing to the AD7482
The AD7482 features a user accessible offset register. This allows
the bottom of the transfer function to be shifted by ±200 mV. This
feature is explained in more detail in the Offset/Overrange section.
To write to the offset register, a 13-bit word is written to the
AD7482 with the 10 LSBs containing the offset value in twos
complement format. The 3 MSBs must be set to 0. The offset
value must be within the range −327 to +327, corresponding to
an offset from −200 mV to +200 mV. The value written to the
offset register is stored and used until power is removed from
the device, or the device is reset. The value stored can be updated at
any time between conversions by another write to the device.
Table 9 shows examples of offset register values and their effective
offset voltage. Figure 30 shows a timing diagram for writing to
the AD7482.
Table 9. Offset Register Examples
Code
(Decimal)
−327
−128
+64
+327
QUIET
. This is the amount of time that must be left
D12 to D10
000
000
000
000
Figure 29
D9 to D0 (Twos
Complement)
1010111001
1110000000
0001000000
0101000111
shows a timing specifica-
Offset
(mV)
−200
−78.12
+39.06
+200
Rev. A | Page 16 of 20
Driving the CONVST Pin
To achieve the specified performance from the AD7482, the
CONVST pin must be driven from a low jitter source. Because
the falling edge on the CONVST pin determines the sampling
instant, any jitter that may exist on this edge appears as noise
when the analog input signal contains high frequency components.
The relationship between the analog input frequency (f
jitter (t
For example, if the desired SNR due to jitter was 100 dB with a
maximum full-scale analog input frequency of 1.5 MHz, ignoring
all other noise sources, the result is an allowable jitter on the
CONVST falling edge of 1.06 ps. For a 12-bit converter (ideal
SNR = 74 dB), the allowable jitter is greater than 1.06 ps, but
due consideration must be given to the design of the CONVST
circuitry to achieve 12-bit performance with large analog input
frequencies.
Typical Connection
Figure 23 shows a typical connection diagram for the AD7482
operating in Parallel Mode 1. Conversion is initiated by a falling
edge on CONVST . When CONVST goes low, the BUSY signal
goes low, and at the end of conversion, the rising edge of BUSY
is used to activate an interrupt service routine. The CS and RD
lines are then activated to read the 12 data bits (13 bits if using
the overrange feature).
In Figure 23, the V
logic output levels being either 0 V or DV
V
example, if DV
by a 3 V supply, the logic output levels are either 0 V or 3 V. This
feature allows the AD7482 to interface to 3 V devices, while still
enabling the ADC to process signals at a 5 V supply.
4.75V TO 5.25V
DRIVE
DIGITAL
SUPPLY
ADM809
SNR
controls the voltage value of the output logic signals. For
j
), and resulting SNR is given by
JITTER
0.1µF
10µF
DD
INTERFACE
+
PARALLEL
( )
dB
Figure 23. Typical Connection Diagram
is supplied by a 5 V supply and V
DRIVE
=
1nF
10
pin is tied to DV
log
V
RESET
MODE1
MODE2
WRITE
CLIP
NAP
STBY
D0 TO D12
CS
CONVST
RD
BUSY
DRIVE
0.1µF
(
2
AD7482
π
DV
×
DD
f
1
IN
REFOUT
REFSEL
AV
×
REFIN
C
DD
t
BIAS
VIN
j
DD
)
DD
2
. The voltage applied to
0.1µF
, which results in
0.47µF
0.47µF
0V TO 2.5V
1nF
DRIVE
+
4.75V TO 5.25V
47µF
IN
ANALOG
REFERENCE
SUPPLY
is supplied
AD780 2.5V
), timing