EVAL-ADV7314EB Analog Devices Inc, EVAL-ADV7314EB Datasheet - Page 36

• Manufacturer Part Number: EVAL-ADV7314EB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7314EB

• Lead Free Status / Rohs Status: Not Compliant

ADV7314
P_HSYNC
1 -> 0
0
0 -> 1
1
1
*When async timing mode is enabled, P_BLANK [Pin 25] becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
HD Timing Reset
[Subaddress 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. On setting this bit back to 0,
the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock
cycle, otherwise this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
P_VSYNC
0
0 -> 1
0 or 1
0 or 1
0 or 1
P_BLANK*
0 or 1
0 or 1
0
0 -> 1
1 -> 0
Table V. Async Timing Mode Truth Table
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
–36–
Reference in
Figures 28a and 28b
a
b
c
d
e
REV. 0