IS41LV16105C-50KLI ISSI, Integrated Silicon Solution Inc, IS41LV16105C-50KLI Datasheet - Page 10

• Manufacturer Part Number: IS41LV16105C-50KLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS41LV16105C-50KLI

• Lead Free Status / Rohs Status: Compliant

IS41C16105C
IS41LV16105C
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (V
Input timing reference levels: V
Output timing reference levels: V
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
3. In addition to meeting the transition rate specification, all input signals must transit between V
4. If CAS and RAS = V
5. If CAS = V
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
8. Assumes that t
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear
1 0. Operation with the t
1 1. Operation within the t
1 2. Either t
1 3. t
1 4. t
1 5. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
1 6. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
1 7. Write command is defined as WE going low.
1 8. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
1 9. The I/Os are in open during READ cycles once t
2 0. The first χCAS edge to transition LOW.
2 1. The last χCAS edge to transition HIGH.
2 2. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
2 3. Last falling χCAS edge to first rising χCAS edge.
2 4. Last rising χCAS edge to next cycle’s last rising χCAS edge.
2 5. Last rising χCAS edge to first falling χCAS edge.
2 6. Each χCAS must meet minimum pulse width.
2 7. Last χCAS to go LOW.
2 8. I/Os controlled, regardless UCAS and LCAS.
2 9. The 3 ns minimum is a parameter guaranteed by design.
3 0. Enables on-chip refresh and address counters.
10
2. V
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
and V
in a monotonic manner.
the amount that t
the data output buffer, CAS and RAS must be pulsed for t
is greater than the specified t
is greater than the specified t
t
t
from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go
back to V
cycle.
LATE WRITE or READ-MODIFY-WRITE is not possible.
ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains
LOW and OE is taken back to LOW after t
MODIFY-WRITE cycles.
off
wcs
wcs
rwd
ih
(MIN) and V
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
, t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
(MIN), t
il
rwd
rch
(or between V
ih
, t
il
or t
) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled)
One TTL Load and 50 pF (V
, data output may contain data from the last valid READ cycle.
awd
awd
rrh
rcd
rcd
and t
il
ž t
rcd
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
must be satisfied for a READ cycle.
t
ž t
awd
rcd
rcd
ih
exceeds the value shown.
rad
rcd
cwd
, data output is High-Z.
il
(MIN) and t
(MAX) limit ensures that t
and V
(MAX). If t
(MAX) limit ensures that t
(MAX).
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
rcd
rad
ih
V
) and assume to be 1 ns for all inputs.
ih
ih
(MAX) limit, access time is controlled exclusively by t
(MAX) limit, access time is controlled exclusively by t
= 2.4V, V
= 2.0V, V
oh
rcd
cwd
= 2.4V, V
is greater than the maximum recommended value shown in this table, t
ž t
cwd
oeh
dd
dd
il
il
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read
= 3.3V ±10%)
is met.
= 0.8V (V
= 0.8V (V
= 5.0V ±10%)
ol
od
rac
= 0.4V (V
rcd
or t
(MAX) can be met. t
(MAX) can be met. t
off
dd
dd
cp
occur.
= 5.0V ±10%);
= 3.3V ±10%)
.
dd
= 5V ±10%, 3.3V ±10%)
od
Integrated Silicon Solution, Inc. — 1-800-379-4774
and t
rcd
rad
oeh
(MAX) is specified as a reference point only; if t
(MAX) is specified as a reference point only; if t
met (OE HIGH during WRITE cycle) in order to
aa
cac
ref
.
.
refresh requirement is exceeded.
ih
and V
il
(or between V
oh
rac
or V
will increase by
ol
il
.
and V
04/09/2010
Rev. 00A
wcs
rwd
rcd
rad
ih
ž
ž
ih
)